[PATCH] D123181: [RISCV] Refactoring the type promotion process of instructions fsl/fsr

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:6589
+  // Deal with the Instruction Operands
+  SmallVector<SDValue, 8> NewOp;
+  // Walk through the operand list.
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8 seems high. Are we ever using more than 3?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123181/new/

https://reviews.llvm.org/D123181