[llvm] e995526 - [AArch64][NFC] Update comment in AArch64.td

[Alexander Shaposhnikov via llvm-commits]

Author: Alexander Shaposhnikov
Date: 2022-04-11T05:36:28Z
New Revision: e995526e661fa5e11c84fc299081c078d9519b3a

URL: https://github.com/llvm/llvm-project/commit/e995526e661fa5e11c84fc299081c078d9519b3a
DIFF: https://github.com/llvm/llvm-project/commit/e995526e661fa5e11c84fc299081c078d9519b3a.diff

LOG: [AArch64][NFC] Update comment in AArch64.td

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 2abf2da6bc700..bd6deb5523f0e 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -1071,11 +1071,12 @@ def ProcessorFeatures {
   // ETE and TRBE are future architecture extensions. We temporarily enable them
   // by default for users targeting generic AArch64. The extensions do not
   // affect code generated by the compiler and can be used only by explicitly
-  // mentioning the new system register names in assembly.
-  list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE, FeatureFuseAdrpAdd];
+  // mentioning the new system register names in assembly. FeatureFuseAdrpAdd is
+  // enabled under Generic to allow linker merging optimizations.
+  list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE,
+                                    FeatureFuseAdrpAdd];
 }
 
-
 def : ProcessorModel<"generic", CortexA55Model, ProcessorFeatures.Generic,
                      [FeatureFuseAES, FeaturePostRAScheduler]>;
 def : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53,