[PATCH] D123406: [RISCV] Only try LUI+SH*ADD+ADDI for int materialization if LUI+ADDI+SH*ADD failed.

[Craig Topper via Phabricator via llvm-commits]

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There's an assert in LUI+SH*ADD+ADDI materialization that makes sure the
lower 12 bits aren't zero since that case should have been handled as
LUI+ADDI+SH*ADD. But nothing prevented the LUI+SH*ADD+ADDI checks from
running after the earlier code handled it.

The sequence would be the same length or longer so it wouldn't replace
the earlier sequence, but the assert happened before that was checked.

The vector holding the sequence also wasn't reset before the second
check so that guaranteed the sequence would never be found to be
shorter.

This patch fixes this by only trying the second expansion when the
earlier fails.

Fixes PR54812.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D123406

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
  llvm/test/CodeGen/RISCV/imm.ll

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