[llvm] 3075e5d - [X86][FastISel] Fix with.overflow + select eflags clobber (PR54369)

[Nikita Popov via llvm-commits]

Author: Nikita Popov
Date: 2022-04-08T16:12:28+02:00
New Revision: 3075e5d2efd04dcd0add0e7f0a0d169fdc255f04

URL: https://github.com/llvm/llvm-project/commit/3075e5d2efd04dcd0add0e7f0a0d169fdc255f04
DIFF: https://github.com/llvm/llvm-project/commit/3075e5d2efd04dcd0add0e7f0a0d169fdc255f04.diff

LOG: [X86][FastISel] Fix with.overflow + select eflags clobber (PR54369)

Don't try to directly use the with.overflow flag result in a cmov
if we need to materialize constants between the instruction
producing the overflow flag and the cmov. The current code is
careful to check that there are no other instructions in between,
but misses the constant materialization case (which may clobber
eflags via xor or constant expression evaluation).

Fixes https://github.com/llvm/llvm-project/issues/54369.

Differential Revision: https://reviews.llvm.org/D122825

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86FastISel.cpp
    llvm/test/CodeGen/X86/pr54369.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp
index 397c61261e3d1..8698cd9c4eb03 100644
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -281,6 +281,11 @@ bool X86FastISel::foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I,
   if (I->isTerminator() && llvm::any_of(successors(I), HasPhis))
     return false;
 
+  // Make sure there are no potentially eflags clobbering constant
+  // materializations in between.
+  if (llvm::any_of(I->operands(), [](Value *V) { return isa<Constant>(V); }))
+    return false;
+
   CC = TmpCC;
   return true;
 }

diff  --git a/llvm/test/CodeGen/X86/pr54369.ll b/llvm/test/CodeGen/X86/pr54369.ll
index ff6094120cf73..b9965abba6701 100644
--- a/llvm/test/CodeGen/X86/pr54369.ll
+++ b/llvm/test/CodeGen/X86/pr54369.ll
@@ -1,16 +1,16 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-- -O0 < %s | FileCheck %s
 
-; FIXME: This is currently miscompiled due to an eflags clobber.
 define i64 @adder(i64 %lhs, i64 %rhs) {
 ; CHECK-LABEL: adder:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addq %rsi, %rdi
-; CHECK-NEXT:    seto %al
+; CHECK-NEXT:    seto %dl
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    # kill: def $rax killed $eax
 ; CHECK-NEXT:    movl $148, %ecx
-; CHECK-NEXT:    cmovoq %rcx, %rax
+; CHECK-NEXT:    testb $1, %dl
+; CHECK-NEXT:    cmovneq %rcx, %rax
 ; CHECK-NEXT:    retq
 	%res = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %lhs, i64 %rhs)
 	%errorbit = extractvalue { i64, i1 } %res, 1
@@ -24,11 +24,12 @@ define i64 @adder_constexpr(i64 %lhs, i64 %rhs) {
 ; CHECK-LABEL: adder_constexpr:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addq %rsi, %rdi
-; CHECK-NEXT:    seto %al
+; CHECK-NEXT:    seto %dl
 ; CHECK-NEXT:    movq a at GOTPCREL(%rip), %rax
 ; CHECK-NEXT:    addq $5, %rax
 ; CHECK-NEXT:    movl $148, %ecx
-; CHECK-NEXT:    cmovoq %rcx, %rax
+; CHECK-NEXT:    testb $1, %dl
+; CHECK-NEXT:    cmovneq %rcx, %rax
 ; CHECK-NEXT:    retq
   %res = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %lhs, i64 %rhs)
   %errorbit = extractvalue { i64, i1 } %res, 1