[llvm] d98bea8 - [RISCV] Add more .vx patterns for VLMax integer setccs.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 7 09:22:27 PDT 2022
Author: Craig Topper
Date: 2022-04-07T09:17:43-07:00
New Revision: d98bea87ef655db811225e1703c2739bf134c566
URL: https://github.com/llvm/llvm-project/commit/d98bea87ef655db811225e1703c2739bf134c566
DIFF: https://github.com/llvm/llvm-project/commit/d98bea87ef655db811225e1703c2739bf134c566.diff
LOG: [RISCV] Add more .vx patterns for VLMax integer setccs.
This patch synchronizes the structure of the templates with those
in RISCVInstrInfoVVLPatterns.td so that we get patterns with .vx
on the left hand side.
Reviewed By: rogfer01
Differential Revision: https://reviews.llvm.org/D123255
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 37b772c465afd..e8b3af40a8d4b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -24,10 +24,6 @@
def rvv_vnot : PatFrag<(ops node:$in),
(xor node:$in, (riscv_vmset_vl (XLenVT srcvalue)))>;
-class SwapHelper<dag Prefix, dag A, dag B, dag Suffix, bit swap> {
- dag Value = !con(Prefix, !if(swap, B, A), !if(swap, A, B), Suffix);
-}
-
multiclass VPatUSLoadStoreSDNode<ValueType type,
int log2sew,
LMULInfo vlmul,
@@ -174,67 +170,70 @@ multiclass VPatBinaryFPSDNode_R_VF<SDNode vop, string instruction_name> {
fvti.AVL, fvti.Log2SEW)>;
}
-multiclass VPatIntegerSetCCSDNode_VV<CondCode cc,
- string instruction_name,
- bit swap = 0> {
+multiclass VPatIntegerSetCCSDNode_VV<string instruction_name,
+ CondCode cc> {
foreach vti = AllIntegerVectors in {
defvar instruction = !cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX);
def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
(vti.Vector vti.RegClass:$rs2), cc)),
- SwapHelper<(instruction),
- (instruction vti.RegClass:$rs1),
- (instruction vti.RegClass:$rs2),
- (instruction vti.AVL, vti.Log2SEW),
- swap>.Value>;
+ (instruction vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL,
+ vti.Log2SEW)>;
+ }
+}
+
+multiclass VPatIntegerSetCCSDNode_VV_Swappable<string instruction_name,
+ CondCode cc, CondCode invcc>
+ : VPatIntegerSetCCSDNode_VV<instruction_name, cc> {
+ foreach vti = AllIntegerVectors in {
+ defvar instruction = !cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX);
+ def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs2),
+ (vti.Vector vti.RegClass:$rs1), invcc)),
+ (instruction vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL,
+ vti.Log2SEW)>;
}
}
-multiclass VPatIntegerSetCCSDNode_XI<CondCode cc,
+multiclass VPatIntegerSetCCSDNode_XI<
string instruction_name,
+ CondCode cc,
string kind,
ComplexPattern SplatPatKind,
- DAGOperand xop_kind,
- bit swap = 0> {
+ DAGOperand xop_kind> {
foreach vti = AllIntegerVectors in {
defvar instruction = !cast<Instruction>(instruction_name#_#kind#_#vti.LMul.MX);
def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
(vti.Vector (SplatPatKind xop_kind:$rs2)), cc)),
- SwapHelper<(instruction),
- (instruction vti.RegClass:$rs1),
- (instruction xop_kind:$rs2),
- (instruction vti.AVL, vti.Log2SEW),
- swap>.Value>;
+ (instruction vti.RegClass:$rs1, xop_kind:$rs2, vti.AVL, vti.Log2SEW)>;
}
}
-multiclass VPatIntegerSetCCSDNode_VV_VX_VI<CondCode cc,
- string instruction_name,
- bit swap = 0> {
- defm : VPatIntegerSetCCSDNode_VV<cc, instruction_name, swap>;
- defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VX",
- SplatPat, GPR, swap>;
- defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VI",
- SplatPat_simm5, simm5, swap>;
+multiclass VPatIntegerSetCCSDNode_XI_Swappable<string instruction_name,
+ CondCode cc, CondCode invcc,
+ string kind,
+ ComplexPattern SplatPatKind,
+ DAGOperand xop_kind>
+ : VPatIntegerSetCCSDNode_XI<instruction_name, cc, kind, SplatPatKind,
+ xop_kind> {
+ foreach vti = AllIntegerVectors in {
+ defvar instruction = !cast<Instruction>(instruction_name#_#kind#_#vti.LMul.MX);
+ def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
+ (vti.Vector (SplatPatKind xop_kind:$rs2)), cc)),
+ (instruction vti.RegClass:$rs1, xop_kind:$rs2, vti.AVL, vti.Log2SEW)>;
+ def : Pat<(vti.Mask (setcc (vti.Vector (SplatPatKind xop_kind:$rs2)),
+ (vti.Vector vti.RegClass:$rs1), invcc)),
+ (instruction vti.RegClass:$rs1, xop_kind:$rs2, vti.AVL, vti.Log2SEW)>;
+ }
}
-multiclass VPatIntegerSetCCSDNode_VV_VX<CondCode cc,
- string instruction_name,
- bit swap = 0> {
- defm : VPatIntegerSetCCSDNode_VV<cc, instruction_name, swap>;
- defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VX",
- SplatPat, GPR, swap>;
-}
+multiclass VPatIntegerSetCCSDNode_VX_Swappable<string instruction_name,
+ CondCode cc, CondCode invcc>
+ : VPatIntegerSetCCSDNode_XI_Swappable<instruction_name, cc, invcc, "VX",
+ SplatPat, GPR>;
-multiclass VPatIntegerSetCCSDNode_VX_VI<CondCode cc,
- string instruction_name,
- bit swap = 0> {
- defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VX",
- SplatPat, GPR, swap>;
- defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VI",
- SplatPat_simm5, simm5, swap>;
-}
+multiclass VPatIntegerSetCCSDNode_VI<string instruction_name, CondCode cc>
+ : VPatIntegerSetCCSDNode_XI<instruction_name, cc, "VI", SplatPat_simm5, simm5>;
-multiclass VPatIntegerSetCCSDNode_VIPlus1<CondCode cc, string instruction_name,
+multiclass VPatIntegerSetCCSDNode_VIPlus1<string instruction_name, CondCode cc,
ComplexPattern splatpat_kind> {
foreach vti = AllIntegerVectors in {
defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX);
@@ -613,29 +612,38 @@ foreach vti = AllIntegerVectors in {
}
// 12.8. Vector Integer Comparison Instructions
-defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETEQ, "PseudoVMSEQ">;
-defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETNE, "PseudoVMSNE">;
-
-defm : VPatIntegerSetCCSDNode_VV_VX<SETLT, "PseudoVMSLT">;
-defm : VPatIntegerSetCCSDNode_VV_VX<SETULT, "PseudoVMSLTU">;
-defm : VPatIntegerSetCCSDNode_VIPlus1<SETLT, "PseudoVMSLE",
+defm : VPatIntegerSetCCSDNode_VV<"PseudoVMSEQ", SETEQ>;
+defm : VPatIntegerSetCCSDNode_VV<"PseudoVMSNE", SETNE>;
+
+defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLT", SETLT, SETGT>;
+defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
+defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLE", SETLE, SETGE>;
+defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
+
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSEQ", SETEQ, SETEQ>;
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSNE", SETNE, SETNE>;
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLT", SETLT, SETGT>;
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLE", SETLE, SETGE>;
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSGT", SETGT, SETLT>;
+defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSGTU", SETUGT, SETULT>;
+// There is no VMSGE(U)_VX instruction
+
+defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSEQ", SETEQ>;
+defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSNE", SETNE>;
+defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSLE", SETLE>;
+defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSLEU", SETULE>;
+defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSGT", SETGT>;
+defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSGTU", SETUGT>;
+
+defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSLE", SETLT,
SplatPat_simm5_plus1_nonzero>;
-defm : VPatIntegerSetCCSDNode_VIPlus1<SETULT, "PseudoVMSLEU",
+defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSLEU", SETULT,
SplatPat_simm5_plus1_nonzero>;
-
-defm : VPatIntegerSetCCSDNode_VV<SETGT, "PseudoVMSLT", /*swap*/1>;
-defm : VPatIntegerSetCCSDNode_VV<SETUGT, "PseudoVMSLTU", /*swap*/1>;
-defm : VPatIntegerSetCCSDNode_VX_VI<SETGT, "PseudoVMSGT">;
-defm : VPatIntegerSetCCSDNode_VX_VI<SETUGT, "PseudoVMSGTU">;
-
-defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETLE, "PseudoVMSLE">;
-defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETULE, "PseudoVMSLEU">;
-
-defm : VPatIntegerSetCCSDNode_VV<SETGE, "PseudoVMSLE", /*swap*/1>;
-defm : VPatIntegerSetCCSDNode_VV<SETUGE, "PseudoVMSLEU", /*swap*/1>;
-defm : VPatIntegerSetCCSDNode_VIPlus1<SETGE, "PseudoVMSGT",
+defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSGT", SETGE,
SplatPat_simm5_plus1>;
-defm : VPatIntegerSetCCSDNode_VIPlus1<SETUGE, "PseudoVMSGTU",
+defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSGTU", SETUGE,
SplatPat_simm5_plus1_nonzero>;
// 12.9. Vector Integer Min/Max Instructions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 487bb43ccad03..ba62cce1ad04b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -464,8 +464,8 @@ multiclass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name,
// Inherits from VPatIntegerSetCCVL_VV and adds a pattern with operands swapped.
multiclass VPatIntegerSetCCVL_VV_Swappable<VTypeInfo vti, string instruction_name,
- CondCode cc, CondCode invcc> :
- VPatIntegerSetCCVL_VV<vti, instruction_name, cc> {
+ CondCode cc, CondCode invcc>
+ : VPatIntegerSetCCVL_VV<vti, instruction_name, cc> {
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2),
vti.RegClass:$rs1, invcc,
(vti.Mask V0),
diff --git a/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
index 0d3984c9448f0..df1fe1a28b381 100644
--- a/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
@@ -50,8 +50,7 @@ define <vscale x 1 x i8> @cttz_nxv1i8(<vscale x 1 x i8> %va) {
; RV32D-LABEL: cttz_nxv1i8:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; RV32D-NEXT: vmv.v.i v9, 0
-; RV32D-NEXT: vmseq.vv v0, v9, v8
+; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
@@ -69,8 +68,7 @@ define <vscale x 1 x i8> @cttz_nxv1i8(<vscale x 1 x i8> %va) {
; RV64D-LABEL: cttz_nxv1i8:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
-; RV64D-NEXT: vmv.v.i v9, 0
-; RV64D-NEXT: vmseq.vv v0, v9, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
@@ -135,8 +133,7 @@ define <vscale x 2 x i8> @cttz_nxv2i8(<vscale x 2 x i8> %va) {
; RV32D-LABEL: cttz_nxv2i8:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; RV32D-NEXT: vmv.v.i v9, 0
-; RV32D-NEXT: vmseq.vv v0, v9, v8
+; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
@@ -154,8 +151,7 @@ define <vscale x 2 x i8> @cttz_nxv2i8(<vscale x 2 x i8> %va) {
; RV64D-LABEL: cttz_nxv2i8:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
-; RV64D-NEXT: vmv.v.i v9, 0
-; RV64D-NEXT: vmseq.vv v0, v9, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vsetvli zero, zero, e32, m1, ta, mu
@@ -220,8 +216,7 @@ define <vscale x 4 x i8> @cttz_nxv4i8(<vscale x 4 x i8> %va) {
; RV32D-LABEL: cttz_nxv4i8:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; RV32D-NEXT: vmv.v.i v9, 0
-; RV32D-NEXT: vmseq.vv v0, v9, v8
+; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -239,8 +234,7 @@ define <vscale x 4 x i8> @cttz_nxv4i8(<vscale x 4 x i8> %va) {
; RV64D-LABEL: cttz_nxv4i8:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
-; RV64D-NEXT: vmv.v.i v9, 0
-; RV64D-NEXT: vmseq.vv v0, v9, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vsetvli zero, zero, e32, m2, ta, mu
@@ -305,8 +299,7 @@ define <vscale x 8 x i8> @cttz_nxv8i8(<vscale x 8 x i8> %va) {
; RV32D-LABEL: cttz_nxv8i8:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; RV32D-NEXT: vmv.v.i v9, 0
-; RV32D-NEXT: vmseq.vv v0, v9, v8
+; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -324,8 +317,7 @@ define <vscale x 8 x i8> @cttz_nxv8i8(<vscale x 8 x i8> %va) {
; RV64D-LABEL: cttz_nxv8i8:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, m1, ta, mu
-; RV64D-NEXT: vmv.v.i v9, 0
-; RV64D-NEXT: vmseq.vv v0, v9, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -390,8 +382,7 @@ define <vscale x 16 x i8> @cttz_nxv16i8(<vscale x 16 x i8> %va) {
; RV32D-LABEL: cttz_nxv16i8:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; RV32D-NEXT: vmv.v.i v10, 0
-; RV32D-NEXT: vmseq.vv v0, v10, v8
+; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v10, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v10
; RV32D-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -409,8 +400,7 @@ define <vscale x 16 x i8> @cttz_nxv16i8(<vscale x 16 x i8> %va) {
; RV64D-LABEL: cttz_nxv16i8:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; RV64D-NEXT: vmv.v.i v10, 0
-; RV64D-NEXT: vmseq.vv v0, v10, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v10, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v10
; RV64D-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -541,8 +531,7 @@ define <vscale x 1 x i16> @cttz_nxv1i16(<vscale x 1 x i16> %va) {
; RV32D-LABEL: cttz_nxv1i16:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; RV32D-NEXT: vmv.v.i v9, 0
-; RV32D-NEXT: vmseq.vv v0, v9, v8
+; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vfwcvt.f.xu.v v9, v8
@@ -556,8 +545,7 @@ define <vscale x 1 x i16> @cttz_nxv1i16(<vscale x 1 x i16> %va) {
; RV64D-LABEL: cttz_nxv1i16:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
-; RV64D-NEXT: vmv.v.i v9, 0
-; RV64D-NEXT: vmseq.vv v0, v9, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v9, v8
@@ -632,8 +620,7 @@ define <vscale x 2 x i16> @cttz_nxv2i16(<vscale x 2 x i16> %va) {
; RV32D-LABEL: cttz_nxv2i16:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; RV32D-NEXT: vmv.v.i v9, 0
-; RV32D-NEXT: vmseq.vv v0, v9, v8
+; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vfwcvt.f.xu.v v9, v8
@@ -647,8 +634,7 @@ define <vscale x 2 x i16> @cttz_nxv2i16(<vscale x 2 x i16> %va) {
; RV64D-LABEL: cttz_nxv2i16:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
-; RV64D-NEXT: vmv.v.i v9, 0
-; RV64D-NEXT: vmseq.vv v0, v9, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v9, v8
@@ -723,8 +709,7 @@ define <vscale x 4 x i16> @cttz_nxv4i16(<vscale x 4 x i16> %va) {
; RV32D-LABEL: cttz_nxv4i16:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; RV32D-NEXT: vmv.v.i v9, 0
-; RV32D-NEXT: vmseq.vv v0, v9, v8
+; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: vfwcvt.f.xu.v v10, v8
@@ -738,8 +723,7 @@ define <vscale x 4 x i16> @cttz_nxv4i16(<vscale x 4 x i16> %va) {
; RV64D-LABEL: cttz_nxv4i16:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, m1, ta, mu
-; RV64D-NEXT: vmv.v.i v9, 0
-; RV64D-NEXT: vmseq.vv v0, v9, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v10, v8
@@ -814,8 +798,7 @@ define <vscale x 8 x i16> @cttz_nxv8i16(<vscale x 8 x i16> %va) {
; RV32D-LABEL: cttz_nxv8i16:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; RV32D-NEXT: vmv.v.i v10, 0
-; RV32D-NEXT: vmseq.vv v0, v10, v8
+; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v10, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v10
; RV32D-NEXT: vfwcvt.f.xu.v v12, v8
@@ -829,8 +812,7 @@ define <vscale x 8 x i16> @cttz_nxv8i16(<vscale x 8 x i16> %va) {
; RV64D-LABEL: cttz_nxv8i16:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, m2, ta, mu
-; RV64D-NEXT: vmv.v.i v10, 0
-; RV64D-NEXT: vmseq.vv v0, v10, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v10, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v10
; RV64D-NEXT: vfwcvt.f.xu.v v12, v8
@@ -905,8 +887,7 @@ define <vscale x 16 x i16> @cttz_nxv16i16(<vscale x 16 x i16> %va) {
; RV32D-LABEL: cttz_nxv16i16:
; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; RV32D-NEXT: vmv.v.i v12, 0
-; RV32D-NEXT: vmseq.vv v0, v12, v8
+; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v12, v8, 0
; RV32D-NEXT: vand.vv v8, v8, v12
; RV32D-NEXT: vfwcvt.f.xu.v v16, v8
@@ -920,8 +901,7 @@ define <vscale x 16 x i16> @cttz_nxv16i16(<vscale x 16 x i16> %va) {
; RV64D-LABEL: cttz_nxv16i16:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e16, m4, ta, mu
-; RV64D-NEXT: vmv.v.i v12, 0
-; RV64D-NEXT: vmseq.vv v0, v12, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v12, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v12
; RV64D-NEXT: vfwcvt.f.xu.v v16, v8
@@ -1077,8 +1057,7 @@ define <vscale x 1 x i32> @cttz_nxv1i32(<vscale x 1 x i32> %va) {
; RV64D-LABEL: cttz_nxv1i32:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
-; RV64D-NEXT: vmv.v.i v9, 0
-; RV64D-NEXT: vmseq.vv v0, v9, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v9, v8
@@ -1177,8 +1156,7 @@ define <vscale x 2 x i32> @cttz_nxv2i32(<vscale x 2 x i32> %va) {
; RV64D-LABEL: cttz_nxv2i32:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m1, ta, mu
-; RV64D-NEXT: vmv.v.i v9, 0
-; RV64D-NEXT: vmseq.vv v0, v9, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v9
; RV64D-NEXT: vfwcvt.f.xu.v v10, v8
@@ -1277,8 +1255,7 @@ define <vscale x 4 x i32> @cttz_nxv4i32(<vscale x 4 x i32> %va) {
; RV64D-LABEL: cttz_nxv4i32:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m2, ta, mu
-; RV64D-NEXT: vmv.v.i v10, 0
-; RV64D-NEXT: vmseq.vv v0, v10, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v10, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v10
; RV64D-NEXT: vfwcvt.f.xu.v v12, v8
@@ -1377,8 +1354,7 @@ define <vscale x 8 x i32> @cttz_nxv8i32(<vscale x 8 x i32> %va) {
; RV64D-LABEL: cttz_nxv8i32:
; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e32, m4, ta, mu
-; RV64D-NEXT: vmv.v.i v12, 0
-; RV64D-NEXT: vmseq.vv v0, v12, v8
+; RV64D-NEXT: vmseq.vx v0, v8, zero
; RV64D-NEXT: vrsub.vi v12, v8, 0
; RV64D-NEXT: vand.vv v8, v8, v12
; RV64D-NEXT: vfwcvt.f.xu.v v16, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
index 64ae9cdd0e19a..a4731700861d2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
@@ -30,8 +30,7 @@ define <vscale x 8 x i1> @icmp_eq_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_eq_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmseq.vv v0, v9, v8
+; CHECK-NEXT: vmseq.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
@@ -101,8 +100,7 @@ define <vscale x 8 x i1> @icmp_ne_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_ne_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmsne.vv v0, v9, v8
+; CHECK-NEXT: vmsne.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
@@ -148,8 +146,7 @@ define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_ugt_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmsltu.vv v0, v8, v9
+; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
@@ -196,8 +193,7 @@ define <vscale x 8 x i1> @icmp_uge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_uge_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmsleu.vv v0, v8, v9
+; CHECK-NEXT: vmsleu.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
@@ -330,8 +326,7 @@ define <vscale x 8 x i1> @icmp_ult_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_ult_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmsltu.vv v0, v9, v8
+; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
@@ -499,8 +494,7 @@ define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_sgt_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmslt.vv v0, v8, v9
+; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
@@ -547,8 +541,7 @@ define <vscale x 8 x i1> @icmp_sge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_sge_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmsle.vv v0, v8, v9
+; CHECK-NEXT: vmsle.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
@@ -643,8 +636,7 @@ define <vscale x 8 x i1> @icmp_slt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
; CHECK-LABEL: icmp_slt_xv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmslt.vv v0, v9, v8
+; CHECK-NEXT: vmsgt.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
@@ -786,8 +778,7 @@ define <vscale x 8 x i1> @icmp_eq_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_eq_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmseq.vv v0, v10, v8
+; CHECK-NEXT: vmseq.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
@@ -857,8 +848,7 @@ define <vscale x 8 x i1> @icmp_ne_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_ne_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmsne.vv v0, v10, v8
+; CHECK-NEXT: vmsne.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
@@ -904,8 +894,7 @@ define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_ugt_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmsltu.vv v0, v8, v10
+; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
@@ -952,8 +941,7 @@ define <vscale x 8 x i1> @icmp_uge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_uge_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmsleu.vv v0, v8, v10
+; CHECK-NEXT: vmsleu.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
@@ -1072,8 +1060,7 @@ define <vscale x 8 x i1> @icmp_ult_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_ult_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmsltu.vv v0, v10, v8
+; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
@@ -1227,8 +1214,7 @@ define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_sgt_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmslt.vv v0, v8, v10
+; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
@@ -1275,8 +1261,7 @@ define <vscale x 8 x i1> @icmp_sge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_sge_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmsle.vv v0, v8, v10
+; CHECK-NEXT: vmsle.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
@@ -1371,8 +1356,7 @@ define <vscale x 8 x i1> @icmp_slt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
; CHECK-LABEL: icmp_slt_xv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmslt.vv v0, v10, v8
+; CHECK-NEXT: vmsgt.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
@@ -1514,8 +1498,7 @@ define <vscale x 8 x i1> @icmp_eq_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_eq_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmseq.vv v0, v12, v8
+; CHECK-NEXT: vmseq.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -1585,8 +1568,7 @@ define <vscale x 8 x i1> @icmp_ne_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_ne_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmsne.vv v0, v12, v8
+; CHECK-NEXT: vmsne.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -1632,8 +1614,7 @@ define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_ugt_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmsltu.vv v0, v8, v12
+; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -1680,8 +1661,7 @@ define <vscale x 8 x i1> @icmp_uge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_uge_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmsleu.vv v0, v8, v12
+; CHECK-NEXT: vmsleu.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -1800,8 +1780,7 @@ define <vscale x 8 x i1> @icmp_ult_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_ult_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmsltu.vv v0, v12, v8
+; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -1955,8 +1934,7 @@ define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_sgt_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmslt.vv v0, v8, v12
+; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -2003,8 +1981,7 @@ define <vscale x 8 x i1> @icmp_sge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_sge_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmsle.vv v0, v8, v12
+; CHECK-NEXT: vmsle.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -2099,8 +2076,7 @@ define <vscale x 8 x i1> @icmp_slt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
; CHECK-LABEL: icmp_slt_xv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmslt.vv v0, v12, v8
+; CHECK-NEXT: vmsgt.vx v0, v8, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -2268,8 +2244,7 @@ define <vscale x 8 x i1> @icmp_eq_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV64-LABEL: icmp_eq_xv_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT: vmv.v.x v16, a0
-; RV64-NEXT: vmseq.vv v0, v16, v8
+; RV64-NEXT: vmseq.vx v0, v8, a0
; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
@@ -2365,8 +2340,7 @@ define <vscale x 8 x i1> @icmp_ne_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV64-LABEL: icmp_ne_xv_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT: vmv.v.x v16, a0
-; RV64-NEXT: vmsne.vv v0, v16, v8
+; RV64-NEXT: vmsne.vx v0, v8, a0
; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
@@ -2438,8 +2412,7 @@ define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV64-LABEL: icmp_ugt_xv_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT: vmv.v.x v16, a0
-; RV64-NEXT: vmsltu.vv v0, v8, v16
+; RV64-NEXT: vmsltu.vx v0, v8, a0
; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
@@ -2512,8 +2485,7 @@ define <vscale x 8 x i1> @icmp_uge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV64-LABEL: icmp_uge_xv_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT: vmv.v.x v16, a0
-; RV64-NEXT: vmsleu.vv v0, v8, v16
+; RV64-NEXT: vmsleu.vx v0, v8, a0
; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
@@ -2658,8 +2630,7 @@ define <vscale x 8 x i1> @icmp_ult_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV64-LABEL: icmp_ult_xv_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT: vmv.v.x v16, a0
-; RV64-NEXT: vmsltu.vv v0, v16, v8
+; RV64-NEXT: vmsgtu.vx v0, v8, a0
; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
@@ -2865,8 +2836,7 @@ define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV64-LABEL: icmp_sgt_xv_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT: vmv.v.x v16, a0
-; RV64-NEXT: vmslt.vv v0, v8, v16
+; RV64-NEXT: vmslt.vx v0, v8, a0
; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
@@ -2939,8 +2909,7 @@ define <vscale x 8 x i1> @icmp_sge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV64-LABEL: icmp_sge_xv_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT: vmv.v.x v16, a0
-; RV64-NEXT: vmsle.vv v0, v8, v16
+; RV64-NEXT: vmsle.vx v0, v8, a0
; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
@@ -3061,8 +3030,7 @@ define <vscale x 8 x i1> @icmp_slt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
; RV64-LABEL: icmp_slt_xv_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT: vmv.v.x v16, a0
-; RV64-NEXT: vmslt.vv v0, v16, v8
+; RV64-NEXT: vmsgt.vx v0, v8, a0
; RV64-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
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