[llvm] 82662b7 - [RISCV] Add swapped patterns to VPatIntegerSetCCVL_VIPlus1.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 7 09:17:22 PDT 2022
Author: Craig Topper
Date: 2022-04-07T09:17:08-07:00
New Revision: 82662b753dbf49b16d2c91b5c15c5cc8bcd78c45
URL: https://github.com/llvm/llvm-project/commit/82662b753dbf49b16d2c91b5c15c5cc8bcd78c45
DIFF: https://github.com/llvm/llvm-project/commit/82662b753dbf49b16d2c91b5c15c5cc8bcd78c45.diff
LOG: [RISCV] Add swapped patterns to VPatIntegerSetCCVL_VIPlus1.
This matches VPatIntegerSetCCVL_VI_Swappable. But as noted in the
FIXME this may only be needed due to lack of canonicalization on
VP_SETCC.
Reviewed By: rogfer01
Differential Revision: https://reviews.llvm.org/D123239
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 7367140df8279..487bb43ccad03 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -502,6 +502,8 @@ multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_nam
(instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1,
XLenVT:$rs2, (vti.Mask V0), GPR:$vl,
vti.Log2SEW)>;
+
+ // FIXME: Can do some canonicalization to remove these patterns.
def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2),
(vti.Vector vti.RegClass:$rs1), invcc,
(vti.Mask V0),
@@ -511,8 +513,10 @@ multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_nam
vti.Log2SEW)>;
}
-multiclass VPatIntegerSetCCVL_VIPlus1<VTypeInfo vti, string instruction_name,
- CondCode cc, ComplexPattern splatpat_kind> {
+multiclass VPatIntegerSetCCVL_VIPlus1_Swappable<VTypeInfo vti,
+ string instruction_name,
+ CondCode cc, CondCode invcc,
+ ComplexPattern splatpat_kind> {
defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK");
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
(splatpat_kind simm5:$rs2), cc,
@@ -521,6 +525,15 @@ multiclass VPatIntegerSetCCVL_VIPlus1<VTypeInfo vti, string instruction_name,
(instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1,
(DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl,
vti.Log2SEW)>;
+
+ // FIXME: Can do some canonicalization to remove these patterns.
+ def : Pat<(vti.Mask (riscv_setcc_vl (splatpat_kind simm5:$rs2),
+ (vti.Vector vti.RegClass:$rs1), invcc,
+ (vti.Mask V0),
+ VLOpFrag)),
+ (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1,
+ (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl,
+ vti.Log2SEW)>;
}
multiclass VPatFPSetCCVL_VV_VF_FV<CondCode cc,
@@ -985,13 +998,13 @@ foreach vti = AllIntegerVectors in {
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>;
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
- defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSLE", SETLT,
+ defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLE", SETLT, SETGT,
SplatPat_simm5_plus1_nonzero>;
- defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSLEU", SETULT,
+ defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLEU", SETULT, SETUGT,
SplatPat_simm5_plus1_nonzero>;
- defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSGT", SETGE,
+ defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGT", SETGE, SETLE,
SplatPat_simm5_plus1>;
- defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSGTU", SETUGE,
+ defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGTU", SETUGE, SETULE,
SplatPat_simm5_plus1_nonzero>;
} // foreach vti = AllIntegerVectors
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
index 6ac1e195ad91f..fcd2331b914c8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
@@ -174,9 +174,8 @@ define <8 x i1> @icmp_ugt_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
define <8 x i1> @icmp_ugt_vi_swap_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_ugt_vi_swap_v8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 4
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vmsltu.vx v0, v8, a1, v0.t
+; CHECK-NEXT: vmsleu.vi v0, v8, 3, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i8> poison, i8 4, i32 0
%vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
@@ -351,9 +350,8 @@ define <8 x i1> @icmp_sgt_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
define <8 x i1> @icmp_sgt_vi_swap_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_sgt_vi_swap_v8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 4
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vmslt.vx v0, v8, a1, v0.t
+; CHECK-NEXT: vmsle.vi v0, v8, 3, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i8> poison, i8 4, i32 0
%vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
@@ -530,10 +528,8 @@ define <8 x i1> @icmp_sle_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
define <8 x i1> @icmp_sle_vi_swap_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_sle_vi_swap_v8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v9, 4
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vmsle.vv v0, v9, v8, v0.t
+; CHECK-NEXT: vmsgt.vi v0, v8, 3, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i8> poison, i8 4, i32 0
%vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
@@ -722,9 +718,8 @@ define <8 x i1> @icmp_ugt_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl)
define <8 x i1> @icmp_ugt_vi_swap_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_ugt_vi_swap_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 4
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vmsltu.vx v10, v8, a1, v0.t
+; CHECK-NEXT: vmsleu.vi v10, v8, 3, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i32> poison, i32 4, i32 0
@@ -914,9 +909,8 @@ define <8 x i1> @icmp_sgt_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl)
define <8 x i1> @icmp_sgt_vi_swap_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_sgt_vi_swap_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 4
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vmslt.vx v10, v8, a1, v0.t
+; CHECK-NEXT: vmsle.vi v10, v8, 3, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i32> poison, i32 4, i32 0
@@ -1108,10 +1102,8 @@ define <8 x i1> @icmp_sle_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl)
define <8 x i1> @icmp_sle_vi_swap_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_sle_vi_swap_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vmv.v.i v12, 4
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vmsle.vv v10, v12, v8, v0.t
+; CHECK-NEXT: vmsgt.vi v10, v8, 3, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i32> poison, i32 4, i32 0
@@ -1391,9 +1383,8 @@ define <8 x i1> @icmp_ugt_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl)
define <8 x i1> @icmp_ugt_vi_swap_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_ugt_vi_swap_v8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 4
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vmsltu.vx v12, v8, a1, v0.t
+; CHECK-NEXT: vmsleu.vi v12, v8, 3, v0.t
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 4, i32 0
@@ -1673,9 +1664,8 @@ define <8 x i1> @icmp_sgt_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl)
define <8 x i1> @icmp_sgt_vi_swap_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_sgt_vi_swap_v8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 4
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vmslt.vx v12, v8, a1, v0.t
+; CHECK-NEXT: vmsle.vi v12, v8, 3, v0.t
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 4, i32 0
@@ -1957,10 +1947,8 @@ define <8 x i1> @icmp_sle_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl)
define <8 x i1> @icmp_sle_vi_swap_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_sle_vi_swap_v8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v16, 4
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vmsle.vv v12, v16, v8, v0.t
+; CHECK-NEXT: vmsgt.vi v12, v8, 3, v0.t
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i64> poison, i64 4, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
index fa4177a489254..32809316fdea3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
@@ -174,9 +174,8 @@ define <vscale x 1 x i1> @icmp_ugt_vi_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1
define <vscale x 1 x i1> @icmp_ugt_vi_swap_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_ugt_vi_swap_nxv1i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 4
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vmsltu.vx v0, v8, a1, v0.t
+; CHECK-NEXT: vmsleu.vi v0, v8, 3, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i8> poison, i8 4, i32 0
%vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
@@ -351,9 +350,8 @@ define <vscale x 1 x i1> @icmp_sgt_vi_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1
define <vscale x 1 x i1> @icmp_sgt_vi_swap_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_sgt_vi_swap_nxv1i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 4
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vmslt.vx v0, v8, a1, v0.t
+; CHECK-NEXT: vmsle.vi v0, v8, 3, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i8> poison, i8 4, i32 0
%vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
@@ -530,10 +528,8 @@ define <vscale x 1 x i1> @icmp_sle_vi_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1
define <vscale x 1 x i1> @icmp_sle_vi_swap_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_sle_vi_swap_nxv1i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.i v9, 4
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vmsle.vv v0, v9, v8, v0.t
+; CHECK-NEXT: vmsgt.vi v0, v8, 3, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i8> poison, i8 4, i32 0
%vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
@@ -708,9 +704,8 @@ define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8
define <vscale x 8 x i1> @icmp_ugt_vi_swap_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_ugt_vi_swap_nxv8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 4
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vmsltu.vx v0, v8, a1, v0.t
+; CHECK-NEXT: vmsleu.vi v0, v8, 3, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i8> poison, i8 4, i32 0
%vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
@@ -885,9 +880,8 @@ define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8
define <vscale x 8 x i1> @icmp_sgt_vi_swap_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_sgt_vi_swap_nxv8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 4
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vmslt.vx v0, v8, a1, v0.t
+; CHECK-NEXT: vmsle.vi v0, v8, 3, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i8> poison, i8 4, i32 0
%vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
@@ -1064,10 +1058,8 @@ define <vscale x 8 x i1> @icmp_sle_vi_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8
define <vscale x 8 x i1> @icmp_sle_vi_swap_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_sle_vi_swap_nxv8i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v9, 4
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vmsle.vv v0, v9, v8, v0.t
+; CHECK-NEXT: vmsgt.vi v0, v8, 3, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i8> poison, i8 4, i32 0
%vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
@@ -1242,9 +1234,8 @@ define <vscale x 1 x i1> @icmp_ugt_vi_nxv1i32(<vscale x 1 x i32> %va, <vscale x
define <vscale x 1 x i1> @icmp_ugt_vi_swap_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_ugt_vi_swap_nxv1i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 4
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vmsltu.vx v0, v8, a1, v0.t
+; CHECK-NEXT: vmsleu.vi v0, v8, 3, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i32> poison, i32 4, i32 0
%vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
@@ -1419,9 +1410,8 @@ define <vscale x 1 x i1> @icmp_sgt_vi_nxv1i32(<vscale x 1 x i32> %va, <vscale x
define <vscale x 1 x i1> @icmp_sgt_vi_swap_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_sgt_vi_swap_nxv1i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 4
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vmslt.vx v0, v8, a1, v0.t
+; CHECK-NEXT: vmsle.vi v0, v8, 3, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i32> poison, i32 4, i32 0
%vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
@@ -1598,10 +1588,8 @@ define <vscale x 1 x i1> @icmp_sle_vi_nxv1i32(<vscale x 1 x i32> %va, <vscale x
define <vscale x 1 x i1> @icmp_sle_vi_swap_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_sle_vi_swap_nxv1i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmv.v.i v9, 4
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vmsle.vv v0, v9, v8, v0.t
+; CHECK-NEXT: vmsgt.vi v0, v8, 3, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i32> poison, i32 4, i32 0
%vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
@@ -1790,9 +1778,8 @@ define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i32(<vscale x 8 x i32> %va, <vscale x
define <vscale x 8 x i1> @icmp_ugt_vi_swap_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_ugt_vi_swap_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 4
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vmsltu.vx v12, v8, a1, v0.t
+; CHECK-NEXT: vmsleu.vi v12, v8, 3, v0.t
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i32> poison, i32 4, i32 0
@@ -1982,9 +1969,8 @@ define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i32(<vscale x 8 x i32> %va, <vscale x
define <vscale x 8 x i1> @icmp_sgt_vi_swap_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_sgt_vi_swap_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 4
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vmslt.vx v12, v8, a1, v0.t
+; CHECK-NEXT: vmsle.vi v12, v8, 3, v0.t
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i32> poison, i32 4, i32 0
@@ -2176,10 +2162,8 @@ define <vscale x 8 x i1> @icmp_sle_vi_nxv8i32(<vscale x 8 x i32> %va, <vscale x
define <vscale x 8 x i1> @icmp_sle_vi_swap_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_sle_vi_swap_nxv8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmv.v.i v16, 4
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vmsle.vv v12, v16, v8, v0.t
+; CHECK-NEXT: vmsgt.vi v12, v8, 3, v0.t
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i32> poison, i32 4, i32 0
@@ -2439,9 +2423,8 @@ define <vscale x 1 x i1> @icmp_ugt_vi_nxv1i64(<vscale x 1 x i64> %va, <vscale x
define <vscale x 1 x i1> @icmp_ugt_vi_swap_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_ugt_vi_swap_nxv1i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 4
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vmsltu.vx v0, v8, a1, v0.t
+; CHECK-NEXT: vmsleu.vi v0, v8, 3, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 4, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
@@ -2700,9 +2683,8 @@ define <vscale x 1 x i1> @icmp_sgt_vi_nxv1i64(<vscale x 1 x i64> %va, <vscale x
define <vscale x 1 x i1> @icmp_sgt_vi_swap_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_sgt_vi_swap_nxv1i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 4
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vmslt.vx v0, v8, a1, v0.t
+; CHECK-NEXT: vmsle.vi v0, v8, 3, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 4, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
@@ -2963,10 +2945,8 @@ define <vscale x 1 x i1> @icmp_sle_vi_nxv1i64(<vscale x 1 x i64> %va, <vscale x
define <vscale x 1 x i1> @icmp_sle_vi_swap_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_sle_vi_swap_nxv1i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v9, 4
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vmsle.vv v0, v9, v8, v0.t
+; CHECK-NEXT: vmsgt.vi v0, v8, 3, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i64> poison, i64 4, i32 0
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
@@ -3245,9 +3225,8 @@ define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i64(<vscale x 8 x i64> %va, <vscale x
define <vscale x 8 x i1> @icmp_ugt_vi_swap_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_ugt_vi_swap_nxv8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 4
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vmsltu.vx v16, v8, a1, v0.t
+; CHECK-NEXT: vmsleu.vi v16, v8, 3, v0.t
; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 4, i32 0
@@ -3527,9 +3506,8 @@ define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i64(<vscale x 8 x i64> %va, <vscale x
define <vscale x 8 x i1> @icmp_sgt_vi_swap_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_sgt_vi_swap_nxv8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 4
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vmslt.vx v16, v8, a1, v0.t
+; CHECK-NEXT: vmsle.vi v16, v8, 3, v0.t
; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 4, i32 0
@@ -3811,10 +3789,8 @@ define <vscale x 8 x i1> @icmp_sle_vi_nxv8i64(<vscale x 8 x i64> %va, <vscale x
define <vscale x 8 x i1> @icmp_sle_vi_swap_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_sle_vi_swap_nxv8i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmv.v.i v24, 4
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vmsle.vv v16, v24, v8, v0.t
+; CHECK-NEXT: vmsgt.vi v16, v8, 3, v0.t
; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x i64> poison, i64 4, i32 0
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