[llvm] 1f6aa90 - [AMDGPU][MC][GFX10] Added syntactic sugar for s_waitcnt_depctr operand
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 7 07:04:42 PDT 2022
Author: Dmitry Preobrazhensky
Date: 2022-04-07T17:03:44+03:00
New Revision: 1f6aa90386b630f85a08fa4c290f944977b98a6d
URL: https://github.com/llvm/llvm-project/commit/1f6aa90386b630f85a08fa4c290f944977b98a6d
DIFF: https://github.com/llvm/llvm-project/commit/1f6aa90386b630f85a08fa4c290f944977b98a6d.diff
LOG: [AMDGPU][MC][GFX10] Added syntactic sugar for s_waitcnt_depctr operand
Added the following helpers:
depctr_hold_cnt(...)
depctr_sa_sdst(...)
depctr_va_vdst(...)
depctr_va_sdst(...)
depctr_va_ssrc(...)
depctr_va_vcc(...)
depctr_vm_vsrc(...)
Differential Revision: https://reviews.llvm.org/D123022
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
llvm/lib/Target/AMDGPU/SIInstrInfo.td
llvm/lib/Target/AMDGPU/SOPInstructions.td
llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
llvm/test/MC/AMDGPU/gfx1030_err.s
llvm/test/MC/AMDGPU/gfx1030_new.s
llvm/test/MC/AMDGPU/sopp-err.s
llvm/test/MC/AMDGPU/sopp-gfx10.s
llvm/test/MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt
llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 34251fde11b64..09681d5409d6e 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -818,6 +818,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
}
bool isSWaitCnt() const;
+ bool isDepCtr() const;
bool isHwreg() const;
bool isSendMsg() const;
bool isSwizzle() const;
@@ -1543,6 +1544,11 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool parseCnt(int64_t &IntVal);
OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);
+
+ bool parseDepCtr(int64_t &IntVal, unsigned &Mask);
+ void depCtrError(SMLoc Loc, int ErrorId, StringRef DepCtrName);
+ OperandMatchResultTy parseDepCtrOps(OperandVector &Operands);
+
OperandMatchResultTy parseHwreg(OperandVector &Operands);
private:
@@ -6333,6 +6339,91 @@ AMDGPUOperand::isSWaitCnt() const {
return isImm();
}
+//===----------------------------------------------------------------------===//
+// DepCtr
+//===----------------------------------------------------------------------===//
+
+void AMDGPUAsmParser::depCtrError(SMLoc Loc, int ErrorId,
+ StringRef DepCtrName) {
+ switch (ErrorId) {
+ case OPR_ID_UNKNOWN:
+ Error(Loc, Twine("invalid counter name ", DepCtrName));
+ return;
+ case OPR_ID_UNSUPPORTED:
+ Error(Loc, Twine(DepCtrName, " is not supported on this GPU"));
+ return;
+ case OPR_ID_DUPLICATE:
+ Error(Loc, Twine("duplicate counter name ", DepCtrName));
+ return;
+ case OPR_VAL_INVALID:
+ Error(Loc, Twine("invalid value for ", DepCtrName));
+ return;
+ default:
+ assert(false);
+ }
+}
+
+bool AMDGPUAsmParser::parseDepCtr(int64_t &DepCtr, unsigned &UsedOprMask) {
+
+ using namespace llvm::AMDGPU::DepCtr;
+
+ SMLoc DepCtrLoc = getLoc();
+ StringRef DepCtrName = getTokenStr();
+
+ if (!skipToken(AsmToken::Identifier, "expected a counter name") ||
+ !skipToken(AsmToken::LParen, "expected a left parenthesis"))
+ return false;
+
+ int64_t ExprVal;
+ if (!parseExpr(ExprVal))
+ return false;
+
+ unsigned PrevOprMask = UsedOprMask;
+ int CntVal = encodeDepCtr(DepCtrName, ExprVal, UsedOprMask, getSTI());
+
+ if (CntVal < 0) {
+ depCtrError(DepCtrLoc, CntVal, DepCtrName);
+ return false;
+ }
+
+ if (!skipToken(AsmToken::RParen, "expected a closing parenthesis"))
+ return false;
+
+ if (trySkipToken(AsmToken::Amp) || trySkipToken(AsmToken::Comma)) {
+ if (isToken(AsmToken::EndOfStatement)) {
+ Error(getLoc(), "expected a counter name");
+ return false;
+ }
+ }
+
+ unsigned CntValMask = PrevOprMask ^ UsedOprMask;
+ DepCtr = (DepCtr & ~CntValMask) | CntVal;
+ return true;
+}
+
+OperandMatchResultTy AMDGPUAsmParser::parseDepCtrOps(OperandVector &Operands) {
+ using namespace llvm::AMDGPU::DepCtr;
+
+ int64_t DepCtr = getDefaultDepCtrEncoding(getSTI());
+ SMLoc Loc = getLoc();
+
+ if (isToken(AsmToken::Identifier) && peekToken().is(AsmToken::LParen)) {
+ unsigned UsedOprMask = 0;
+ while (!isToken(AsmToken::EndOfStatement)) {
+ if (!parseDepCtr(DepCtr, UsedOprMask))
+ return MatchOperand_ParseFail;
+ }
+ } else {
+ if (!parseExpr(DepCtr))
+ return MatchOperand_ParseFail;
+ }
+
+ Operands.push_back(AMDGPUOperand::CreateImm(this, DepCtr, Loc));
+ return MatchOperand_Success;
+}
+
+bool AMDGPUOperand::isDepCtr() const { return isS16Imm(); }
+
//===----------------------------------------------------------------------===//
// hwreg
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 50a733229f329..5622fb785bbcb 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -1438,6 +1438,33 @@ void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
}
}
+void AMDGPUInstPrinter::printDepCtr(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+ using namespace llvm::AMDGPU::DepCtr;
+
+ uint64_t Imm16 = MI->getOperand(OpNo).getImm() & 0xffff;
+
+ bool HasNonDefaultVal = false;
+ if (isSymbolicDepCtrEncoding(Imm16, HasNonDefaultVal, STI)) {
+ int Id = 0;
+ StringRef Name;
+ unsigned Val;
+ bool IsDefault;
+ bool NeedSpace = false;
+ while (decodeDepCtr(Imm16, Id, Name, Val, IsDefault, STI)) {
+ if (!IsDefault || !HasNonDefaultVal) {
+ if (NeedSpace)
+ O << ' ';
+ O << Name << '(' << Val << ')';
+ NeedSpace = true;
+ }
+ }
+ } else {
+ O << formatHex(Imm16);
+ }
+}
+
void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) {
unsigned Id;
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
index 71db0beba0b69..1b3b5d3b1fb00 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
@@ -234,6 +234,8 @@ class AMDGPUInstPrinter : public MCInstPrinter {
raw_ostream &O);
void printWaitFlag(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
+ void printDepCtr(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+ raw_ostream &O);
void printHwreg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
void printEndpgm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 787814172135f..ba4a90e7cab02 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -1016,6 +1016,12 @@ def SWaitMatchClass : AsmOperandClass {
let ParserMethod = "parseSWaitCntOps";
}
+def DepCtrMatchClass : AsmOperandClass {
+ let Name = "DepCtr";
+ let RenderMethod = "addImmOperands";
+ let ParserMethod = "parseDepCtrOps";
+}
+
def VReg32OrOffClass : AsmOperandClass {
let Name = "VReg32OrOff";
let ParserMethod = "parseVReg32OrOff";
@@ -1041,6 +1047,11 @@ def WAIT_FLAG : Operand <i32> {
let ParserMatchClass = SWaitMatchClass;
let PrintMethod = "printWaitFlag";
}
+
+def DepCtrImm : Operand <i32> {
+ let ParserMatchClass = DepCtrMatchClass;
+ let PrintMethod = "printDepCtr";
+}
} // End OperandType = "OPERAND_IMMEDIATE"
include "SIInstrFormats.td"
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index 16f747a285d6d..be2a4d386e7be 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -1343,7 +1343,7 @@ let SubtargetPredicate = isGFX10Plus in {
let fixed_imm = 1;
}
def S_WAITCNT_DEPCTR :
- SOPP_Pseudo <"s_waitcnt_depctr" , (ins s16imm:$simm16), "$simm16">;
+ SOPP_Pseudo <"s_waitcnt_depctr" , (ins DepCtrImm:$simm16), "$simm16">;
let hasSideEffects = 0, Uses = [MODE], Defs = [MODE] in {
def S_ROUND_MODE :
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
index a26390b1270b7..bd1d6dd194e28 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
@@ -11,6 +11,27 @@
namespace llvm {
namespace AMDGPU {
+
+namespace DepCtr {
+
+// NOLINTBEGIN
+const CustomOperandVal DepCtrInfo[] = {
+ // Name max dflt offset width constraint
+ {{"depctr_hold_cnt"}, 1, 1, 7, 1, isGFX10_BEncoding},
+ {{"depctr_sa_sdst"}, 1, 1, 0, 1},
+ {{"depctr_va_vdst"}, 15, 15, 12, 4},
+ {{"depctr_va_sdst"}, 7, 7, 9, 3},
+ {{"depctr_va_ssrc"}, 1, 1, 8, 1},
+ {{"depctr_va_vcc"}, 1, 1, 1, 1},
+ {{"depctr_vm_vsrc"}, 7, 7, 2, 3},
+};
+// NOLINTEND
+
+const int DEP_CTR_SIZE =
+ static_cast<int>(sizeof(DepCtrInfo) / sizeof(CustomOperandVal));
+
+} // namespace DepCtr
+
namespace SendMsg {
// Disable lint checking for this block since it makes the table unreadable.
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h
index 32b439d498b04..92eb37f18d964 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h
@@ -22,6 +22,8 @@ namespace AMDGPU {
const int OPR_ID_UNKNOWN = -1;
const int OPR_ID_UNSUPPORTED = -2;
+const int OPR_ID_DUPLICATE = -3;
+const int OPR_VAL_INVALID = -4;
template <class T> struct CustomOperand {
StringLiteral Name;
@@ -29,6 +31,35 @@ template <class T> struct CustomOperand {
bool (*Cond)(T Context) = nullptr;
};
+struct CustomOperandVal {
+ StringLiteral Name;
+ unsigned Max;
+ unsigned Default;
+ unsigned Shift;
+ unsigned Width;
+ bool (*Cond)(const MCSubtargetInfo &STI) = nullptr;
+ unsigned Mask = (1 << Width) - 1;
+
+ unsigned decode(unsigned Code) const { return (Code >> Shift) & Mask; }
+
+ unsigned encode(unsigned Val) const { return (Val & Mask) << Shift; }
+
+ unsigned getMask() const { return Mask << Shift; }
+
+ bool isValid(unsigned Val) const { return Val <= Max; }
+
+ bool isSupported(const MCSubtargetInfo &STI) const {
+ return !Cond || Cond(STI);
+ }
+};
+
+namespace DepCtr {
+
+extern const CustomOperandVal DepCtrInfo[];
+extern const int DEP_CTR_SIZE;
+
+} // namespace DepCtr
+
namespace SendMsg { // Symbolic names for the sendmsg(...) syntax.
extern const CustomOperand<const MCSubtargetInfo &> Msg[];
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 7c1abf99e2a3d..5984a77b524e2 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -1091,6 +1091,120 @@ static int getOprIdx(int Id, const CustomOperand<T> OpInfo[], int OpInfoSize,
return getOprIdx<T>(Test, OpInfo, OpInfoSize, Context);
}
+//===----------------------------------------------------------------------===//
+// Custom Operand Values
+//===----------------------------------------------------------------------===//
+
+static unsigned getDefaultCustomOperandEncoding(const CustomOperandVal *Opr,
+ int Size,
+ const MCSubtargetInfo &STI) {
+ unsigned Enc = 0;
+ for (int Idx = 0; Idx < Size; ++Idx) {
+ const auto &Op = Opr[Idx];
+ if (Op.isSupported(STI))
+ Enc |= Op.encode(Op.Default);
+ }
+ return Enc;
+}
+
+static bool isSymbolicCustomOperandEncoding(const CustomOperandVal *Opr,
+ int Size, unsigned Code,
+ bool &HasNonDefaultVal,
+ const MCSubtargetInfo &STI) {
+ unsigned UsedOprMask = 0;
+ HasNonDefaultVal = false;
+ for (int Idx = 0; Idx < Size; ++Idx) {
+ const auto &Op = Opr[Idx];
+ if (!Op.isSupported(STI))
+ continue;
+ UsedOprMask |= Op.getMask();
+ unsigned Val = Op.decode(Code);
+ if (!Op.isValid(Val))
+ return false;
+ HasNonDefaultVal |= (Val != Op.Default);
+ }
+ return (Code & ~UsedOprMask) == 0;
+}
+
+static bool decodeCustomOperand(const CustomOperandVal *Opr, int Size,
+ unsigned Code, int &Idx, StringRef &Name,
+ unsigned &Val, bool &IsDefault,
+ const MCSubtargetInfo &STI) {
+ while (Idx < Size) {
+ const auto &Op = Opr[Idx++];
+ if (Op.isSupported(STI)) {
+ Name = Op.Name;
+ Val = Op.decode(Code);
+ IsDefault = (Val == Op.Default);
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static int encodeCustomOperandVal(const CustomOperandVal &Op,
+ int64_t InputVal) {
+ if (InputVal < 0 || InputVal > Op.Max)
+ return OPR_VAL_INVALID;
+ return Op.encode(InputVal);
+}
+
+static int encodeCustomOperand(const CustomOperandVal *Opr, int Size,
+ const StringRef Name, int64_t InputVal,
+ unsigned &UsedOprMask,
+ const MCSubtargetInfo &STI) {
+ int InvalidId = OPR_ID_UNKNOWN;
+ for (int Idx = 0; Idx < Size; ++Idx) {
+ const auto &Op = Opr[Idx];
+ if (Op.Name == Name) {
+ if (!Op.isSupported(STI)) {
+ InvalidId = OPR_ID_UNSUPPORTED;
+ continue;
+ }
+ auto OprMask = Op.getMask();
+ if (OprMask & UsedOprMask)
+ return OPR_ID_DUPLICATE;
+ UsedOprMask |= OprMask;
+ return encodeCustomOperandVal(Op, InputVal);
+ }
+ }
+ return InvalidId;
+}
+
+//===----------------------------------------------------------------------===//
+// DepCtr
+//===----------------------------------------------------------------------===//
+
+namespace DepCtr {
+
+int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI) {
+ static int Default = -1;
+ if (Default == -1)
+ Default = getDefaultCustomOperandEncoding(DepCtrInfo, DEP_CTR_SIZE, STI);
+ return Default;
+}
+
+bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
+ const MCSubtargetInfo &STI) {
+ return isSymbolicCustomOperandEncoding(DepCtrInfo, DEP_CTR_SIZE, Code,
+ HasNonDefaultVal, STI);
+}
+
+bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
+ bool &IsDefault, const MCSubtargetInfo &STI) {
+ return decodeCustomOperand(DepCtrInfo, DEP_CTR_SIZE, Code, Id, Name, Val,
+ IsDefault, STI);
+}
+
+int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
+ const MCSubtargetInfo &STI) {
+ return encodeCustomOperand(DepCtrInfo, DEP_CTR_SIZE, Name, Val, UsedOprMask,
+ STI);
+}
+
+} // namespace DepCtr
+
//===----------------------------------------------------------------------===//
// hwreg
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index cf5f067eee039..fdbd8080beecf 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -639,6 +639,18 @@ void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
} // namespace Hwreg
+namespace DepCtr {
+
+int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI);
+int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
+ const MCSubtargetInfo &STI);
+bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
+ const MCSubtargetInfo &STI);
+bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
+ bool &IsDefault, const MCSubtargetInfo &STI);
+
+} // namespace DepCtr
+
namespace Exp {
bool getTgtName(unsigned Id, StringRef &Name, int &Index);
diff --git a/llvm/test/MC/AMDGPU/gfx1030_err.s b/llvm/test/MC/AMDGPU/gfx1030_err.s
index 11446e97ce7f8..0b005bc8eed5e 100644
--- a/llvm/test/MC/AMDGPU/gfx1030_err.s
+++ b/llvm/test/MC/AMDGPU/gfx1030_err.s
@@ -152,3 +152,58 @@ image_msaa_load v[1:4], v5, s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D
image_msaa_load v5, v[1:2], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_2D d16
// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dim; must be MSAA type
+
+//===----------------------------------------------------------------------===//
+// s_waitcnt_depctr.
+//===----------------------------------------------------------------------===//
+
+s_waitcnt_depctr depctr_hold_cnt(-1)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_hold_cnt
+
+s_waitcnt_depctr depctr_sa_sdst(-1)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_sa_sdst
+
+s_waitcnt_depctr depctr_va_vdst(-1)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_vdst
+
+s_waitcnt_depctr depctr_va_sdst(-1)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_sdst
+
+s_waitcnt_depctr depctr_va_ssrc(-1)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_ssrc
+
+s_waitcnt_depctr depctr_va_vcc(-1)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_vcc
+
+s_waitcnt_depctr depctr_vm_vsrc(-1)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_vm_vsrc
+
+s_waitcnt_depctr depctr_hold_cnt(2)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_hold_cnt
+
+s_waitcnt_depctr depctr_sa_sdst(2)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_sa_sdst
+
+s_waitcnt_depctr depctr_va_vdst(16)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_vdst
+
+s_waitcnt_depctr depctr_va_sdst(8)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_sdst
+
+s_waitcnt_depctr depctr_va_ssrc(2)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_ssrc
+
+s_waitcnt_depctr depctr_va_vcc(2)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_va_vcc
+
+s_waitcnt_depctr depctr_vm_vsrc(8)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid value for depctr_vm_vsrc
+
+s_waitcnt_depctr depctr_vm_(8)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid counter name depctr_vm_
+
+s_waitcnt_depctr depctr_hold_cnt(0) depctr_hold_cnt(0)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: duplicate counter name depctr_hold_cnt
+
+s_waitcnt_depctr depctr_sa_sdst(0) depctr_sa_sdst(0)
+// GFX10: :[[@LINE-1]]:{{[0-9]+}}: error: duplicate counter name depctr_sa_sdst
diff --git a/llvm/test/MC/AMDGPU/gfx1030_new.s b/llvm/test/MC/AMDGPU/gfx1030_new.s
index f693ccdf3b3fb..08501d9a3ac0a 100644
--- a/llvm/test/MC/AMDGPU/gfx1030_new.s
+++ b/llvm/test/MC/AMDGPU/gfx1030_new.s
@@ -122,3 +122,85 @@ image_msaa_load v[1:4], v[5:8], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
image_msaa_load v14, [v204,v11,v14,v19], s[40:47] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
// GFX10: encoding: [0x3b,0x01,0x00,0xf0,0xcc,0x0e,0x0a,0x00,0x0b,0x0e,0x13,0x00]
+
+//===----------------------------------------------------------------------===//
+// s_waitcnt_depctr.
+//===----------------------------------------------------------------------===//
+
+s_waitcnt_depctr -32768
+// GFX10: encoding: [0x00,0x80,0xa3,0xbf]
+
+s_waitcnt_depctr 65535
+// GFX10: encoding: [0xff,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_hold_cnt(0)
+// GFX10: encoding: [0x1f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_hold_cnt(1)
+// GFX10: encoding: [0x9f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_sa_sdst(0)
+// GFX10: encoding: [0x9e,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_sa_sdst(1)
+// GFX10: encoding: [0x9f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vdst(0)
+// GFX10: encoding: [0x9f,0x0f,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vdst(1)
+// GFX10: encoding: [0x9f,0x1f,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vdst(14)
+// GFX10: encoding: [0x9f,0xef,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vdst(15)
+// GFX10: encoding: [0x9f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_sdst(0)
+// GFX10: encoding: [0x9f,0xf1,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_sdst(1)
+// GFX10: encoding: [0x9f,0xf3,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_sdst(6)
+// GFX10: encoding: [0x9f,0xfd,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_sdst(7)
+// GFX10: encoding: [0x9f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_ssrc(0)
+// GFX10: encoding: [0x9f,0xfe,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_ssrc(1)
+// GFX10: encoding: [0x9f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vcc(0)
+// GFX10: encoding: [0x9d,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vcc(1)
+// GFX10: encoding: [0x9f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_vm_vsrc(0)
+// GFX10: encoding: [0x83,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_vm_vsrc(1)
+// GFX10: encoding: [0x87,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_vm_vsrc(6)
+// GFX10: encoding: [0x9b,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_vm_vsrc(7)
+// GFX10: encoding: [0x9f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_hold_cnt(0) depctr_sa_sdst(0) depctr_va_vdst(0) depctr_va_sdst(0) depctr_va_ssrc(0) depctr_va_vcc(0) depctr_vm_vsrc(0)
+// GFX10: encoding: [0x00,0x00,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_hold_cnt(1) depctr_sa_sdst(1) depctr_va_vdst(15) depctr_va_sdst(7) depctr_va_ssrc(1) depctr_va_vcc(1) depctr_vm_vsrc(7)
+// GFX10: encoding: [0x9f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_hold_cnt(1) & depctr_sa_sdst(1) & depctr_va_vdst(1) & depctr_va_sdst(1) & depctr_va_ssrc(1) & depctr_va_vcc(1) & depctr_vm_vsrc(1)
+// GFX10: encoding: [0x87,0x13,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_hold_cnt(1), depctr_sa_sdst(1), depctr_va_vdst(14), depctr_va_sdst(6), depctr_va_ssrc(1), depctr_va_vcc(1), depctr_vm_vsrc(6)
+// GFX10: encoding: [0x9b,0xed,0xa3,0xbf]
diff --git a/llvm/test/MC/AMDGPU/sopp-err.s b/llvm/test/MC/AMDGPU/sopp-err.s
index c432b0425b4d6..037a6397f314f 100644
--- a/llvm/test/MC/AMDGPU/sopp-err.s
+++ b/llvm/test/MC/AMDGPU/sopp-err.s
@@ -1,6 +1,6 @@
-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck --check-prefixes=GCN,SICI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --check-prefixes=GCN,SICI --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck --check-prefixes=GCN,VI --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck --check-prefixes=GCN,SICI,SICIVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --check-prefixes=GCN,SICI,SICIVI --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck --check-prefixes=GCN,VI,SICIVI --implicit-check-not=error: %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck --check-prefixes=GCN,GFX10 --implicit-check-not=error: %s
//===----------------------------------------------------------------------===//
@@ -197,6 +197,154 @@ s_waitcnt x
s_waitcnt vmcnt(0
// GCN: error: expected a closing parenthesis
+//===----------------------------------------------------------------------===//
+// s_waitcnt_depctr.
+//===----------------------------------------------------------------------===//
+
+s_waitcnt_depctr 65536
+// GFX10: error: invalid operand for instruction
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr -32769
+// GFX10: error: invalid operand for instruction
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_hold_cnt(0)
+// GFX10: error: depctr_hold_cnt is not supported on this GPU
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_sa_sdst(-1)
+// GFX10: error: invalid value for depctr_sa_sdst
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_vdst(-1)
+// GFX10: error: invalid value for depctr_va_vdst
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_sdst(-1)
+// GFX10: error: invalid value for depctr_va_sdst
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_ssrc(-1)
+// GFX10: error: invalid value for depctr_va_ssrc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_vcc(-1)
+// GFX10: error: invalid value for depctr_va_vcc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_vm_vsrc(-1)
+// GFX10: error: invalid value for depctr_vm_vsrc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_sa_sdst(2)
+// GFX10: error: invalid value for depctr_sa_sdst
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_vdst(16)
+// GFX10: error: invalid value for depctr_va_vdst
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_sdst(8)
+// GFX10: error: invalid value for depctr_va_sdst
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_ssrc(2)
+// GFX10: error: invalid value for depctr_va_ssrc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_vcc(2)
+// GFX10: error: invalid value for depctr_va_vcc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_vm_vsrc(8)
+// GFX10: error: invalid value for depctr_vm_vsrc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_vm_(8)
+// GFX10: error: invalid counter name depctr_vm_
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_sa_sdst(0) depctr_sa_sdst(0)
+// GFX10: error: duplicate counter name depctr_sa_sdst
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_vdst(0) depctr_va_vdst(0)
+// GFX10: error: duplicate counter name depctr_va_vdst
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_sdst(0) depctr_va_sdst(0)
+// GFX10: error: duplicate counter name depctr_va_sdst
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_ssrc(0) depctr_va_ssrc(0)
+// GFX10: error: duplicate counter name depctr_va_ssrc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_vcc(0) depctr_va_vcc(0)
+// GFX10: error: duplicate counter name depctr_va_vcc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_vm_vsrc(0) depctr_vm_vsrc(0)
+// GFX10: error: duplicate counter name depctr_vm_vsrc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_sa_sdst(0) depctr_va_sdst(0) depctr_sa_sdst(0)
+// GFX10: error: duplicate counter name depctr_sa_sdst
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_ssrc(0) depctr_va_sdst(0) depctr_va_ssrc(0)
+// GFX10: error: duplicate counter name depctr_va_ssrc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_vcc(0) depctr_va_vcc(0) depctr_va_sdst(0)
+// GFX10: error: duplicate counter name depctr_va_vcc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_vm_vsrc(0) depctr_vm_vsrc(0) depctr_va_sdst(0)
+// GFX10: error: duplicate counter name depctr_vm_vsrc
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_sdst(0) depctr_vm_vsrc 0)
+// GFX10: error: expected a left parenthesis
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_sdst(0) 0depctr_vm_vsrc(0)
+// GFX10: error: expected a counter name
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_sdst(0) depctr_vm_vsrc(x)
+// GFX10: error: expected absolute expression
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_va_sdst(0) depctr_vm_vsrc(0; & depctr_va_sdst(0)
+// GFX10: error: expected a closing parenthesis
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_vm_vsrc 0) depctr_vm_vsrc(0) depctr_va_sdst(0)
+// GFX10: error: expected absolute expression
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_vm_vsrc(0) ,
+// GFX10: error: expected a counter name
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_vm_vsrc(0) , &
+// GFX10: error: expected a counter name
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_vm_vsrc(0) &
+// GFX10: error: expected a counter name
+// SICIVI: error: instruction not supported on this GPU
+
+s_waitcnt_depctr depctr_vm_vsrc(0) & &
+// GFX10: error: expected a counter name
+// SICIVI: error: instruction not supported on this GPU
+
+//===----------------------------------------------------------------------===//
+// s_branch.
+//===----------------------------------------------------------------------===//
+
s_branch 0x80000000ffff
// GCN: error: expected a 16-bit signed jump offset
diff --git a/llvm/test/MC/AMDGPU/sopp-gfx10.s b/llvm/test/MC/AMDGPU/sopp-gfx10.s
index ea5388036327a..eb08a60971934 100644
--- a/llvm/test/MC/AMDGPU/sopp-gfx10.s
+++ b/llvm/test/MC/AMDGPU/sopp-gfx10.s
@@ -21,3 +21,91 @@ s_sendmsg 11
s_sendmsg sendmsg(MSG_GET_DDID)
// GFX10: s_sendmsg sendmsg(MSG_GET_DDID) ; encoding: [0x0b,0x00,0x90,0xbf]
+
+//===----------------------------------------------------------------------===//
+// s_waitcnt_depctr
+//===----------------------------------------------------------------------===//
+
+s_waitcnt_depctr 0x0
+// GFX10: encoding: [0x00,0x00,0xa3,0xbf]
+
+s_waitcnt_depctr -32768
+// GFX10: encoding: [0x00,0x80,0xa3,0xbf]
+
+s_waitcnt_depctr -1
+// GFX10: encoding: [0xff,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr 65535
+// GFX10: encoding: [0xff,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr 0xffff
+// GFX10: encoding: [0xff,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_sa_sdst(0)
+// GFX10: s_waitcnt_depctr depctr_sa_sdst(0) ; encoding: [0x1e,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_sa_sdst(1)
+// GFX10: s_waitcnt_depctr depctr_sa_sdst(1) depctr_va_vdst(15) depctr_va_sdst(7) depctr_va_ssrc(1) depctr_va_vcc(1) depctr_vm_vsrc(7) ; encoding: [0x1f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vdst(0)
+// GFX10: s_waitcnt_depctr depctr_va_vdst(0) ; encoding: [0x1f,0x0f,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vdst(1)
+// GFX10: s_waitcnt_depctr depctr_va_vdst(1) ; encoding: [0x1f,0x1f,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vdst(14)
+// GFX10: s_waitcnt_depctr depctr_va_vdst(14) ; encoding: [0x1f,0xef,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vdst(15)
+// GFX10: s_waitcnt_depctr depctr_sa_sdst(1) depctr_va_vdst(15) depctr_va_sdst(7) depctr_va_ssrc(1) depctr_va_vcc(1) depctr_vm_vsrc(7) ; encoding: [0x1f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_sdst(0)
+// GFX10: s_waitcnt_depctr depctr_va_sdst(0) ; encoding: [0x1f,0xf1,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_sdst(1)
+// GFX10: s_waitcnt_depctr depctr_va_sdst(1) ; encoding: [0x1f,0xf3,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_sdst(6)
+// GFX10: s_waitcnt_depctr depctr_va_sdst(6) ; encoding: [0x1f,0xfd,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_sdst(7)
+// GFX10: s_waitcnt_depctr depctr_sa_sdst(1) depctr_va_vdst(15) depctr_va_sdst(7) depctr_va_ssrc(1) depctr_va_vcc(1) depctr_vm_vsrc(7) ; encoding: [0x1f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_ssrc(0)
+// GFX10: s_waitcnt_depctr depctr_va_ssrc(0) ; encoding: [0x1f,0xfe,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_ssrc(1)
+// GFX10: s_waitcnt_depctr depctr_sa_sdst(1) depctr_va_vdst(15) depctr_va_sdst(7) depctr_va_ssrc(1) depctr_va_vcc(1) depctr_vm_vsrc(7) ; encoding: [0x1f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vcc(0)
+// GFX10: s_waitcnt_depctr depctr_va_vcc(0) ; encoding: [0x1d,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vcc(1)
+// GFX10: s_waitcnt_depctr depctr_sa_sdst(1) depctr_va_vdst(15) depctr_va_sdst(7) depctr_va_ssrc(1) depctr_va_vcc(1) depctr_vm_vsrc(7) ; encoding: [0x1f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_vm_vsrc(0)
+// GFX10: s_waitcnt_depctr depctr_vm_vsrc(0) ; encoding: [0x03,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_vm_vsrc(1)
+// GFX10: s_waitcnt_depctr depctr_vm_vsrc(1) ; encoding: [0x07,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_vm_vsrc(6)
+// GFX10: s_waitcnt_depctr depctr_vm_vsrc(6) ; encoding: [0x1b,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_vm_vsrc(7)
+// GFX10: s_waitcnt_depctr depctr_sa_sdst(1) depctr_va_vdst(15) depctr_va_sdst(7) depctr_va_ssrc(1) depctr_va_vcc(1) depctr_vm_vsrc(7) ; encoding: [0x1f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_sa_sdst(0) depctr_va_vdst(0) depctr_va_sdst(0) depctr_va_ssrc(0) depctr_va_vcc(0) depctr_vm_vsrc(0)
+// GFX10: s_waitcnt_depctr depctr_sa_sdst(0) depctr_va_vdst(0) depctr_va_sdst(0) depctr_va_ssrc(0) depctr_va_vcc(0) depctr_vm_vsrc(0) ; encoding: [0x00,0x00,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_sa_sdst(1) depctr_va_vdst(15) depctr_va_sdst(7) depctr_va_ssrc(1) depctr_va_vcc(1) depctr_vm_vsrc(7)
+// GFX10: s_waitcnt_depctr depctr_sa_sdst(1) depctr_va_vdst(15) depctr_va_sdst(7) depctr_va_ssrc(1) depctr_va_vcc(1) depctr_vm_vsrc(7) ; encoding: [0x1f,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_sa_sdst(1) & depctr_va_vdst(1) & depctr_va_sdst(1) & depctr_va_ssrc(1) & depctr_va_vcc(1) & depctr_vm_vsrc(1)
+// GFX10: s_waitcnt_depctr depctr_va_vdst(1) depctr_va_sdst(1) depctr_vm_vsrc(1) ; encoding: [0x07,0x13,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_sa_sdst(1), depctr_va_vdst(14), depctr_va_sdst(6), depctr_va_ssrc(1), depctr_va_vcc(1), depctr_vm_vsrc(6)
+// GFX10: s_waitcnt_depctr depctr_va_vdst(14) depctr_va_sdst(6) depctr_vm_vsrc(6) ; encoding: [0x1b,0xed,0xa3,0xbf]
+
+s_waitcnt_depctr depctr_va_vdst(14) depctr_va_sdst(6) depctr_vm_vsrc(6)
+// GFX10: s_waitcnt_depctr depctr_va_vdst(14) depctr_va_sdst(6) depctr_vm_vsrc(6) ; encoding: [0x1b,0xed,0xa3,0xbf]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt
index b668f9292a711..92a0b0ccd3bc3 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt
@@ -185,3 +185,64 @@
# GFX10: scratch_store_short_d16_hi off, v2, off ; encoding: [0x00,0x40,0x6c,0xdc,0x00,0x02,0x7f,0x00]
0x00,0x40,0x6c,0xdc,0x00,0x02,0x7f,0x00
+
+#===------------------------------------------------------------------------===#
+# s_waitcnt_depctr.
+#===------------------------------------------------------------------------===#
+
+# GFX10: s_waitcnt_depctr 0x20 ; encoding: [0x20,0x00,0xa3,0xbf]
+0x20,0x00,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr 0x40 ; encoding: [0x40,0x00,0xa3,0xbf]
+0x40,0x00,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr 0x60 ; encoding: [0x60,0x00,0xa3,0xbf]
+0x60,0x00,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr 0xffff ; encoding: [0xff,0xff,0xa3,0xbf]
+0xff,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_hold_cnt(0) ; encoding: [0x1f,0xff,0xa3,0xbf]
+0x1f,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_sa_sdst(0) ; encoding: [0x9e,0xff,0xa3,0xbf]
+0x9e,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vdst(0) ; encoding: [0x9f,0x0f,0xa3,0xbf]
+0x9f,0x0f,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vdst(1) ; encoding: [0x9f,0x1f,0xa3,0xbf]
+0x9f,0x1f,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vdst(14) ; encoding: [0x9f,0xef,0xa3,0xbf]
+0x9f,0xef,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_sdst(0) ; encoding: [0x9f,0xf1,0xa3,0xbf]
+0x9f,0xf1,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_sdst(6) ; encoding: [0x9f,0xfd,0xa3,0xbf]
+0x9f,0xfd,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_ssrc(0) ; encoding: [0x9f,0xfe,0xa3,0xbf]
+0x9f,0xfe,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vcc(0) ; encoding: [0x9d,0xff,0xa3,0xbf]
+0x9d,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_vm_vsrc(0) ; encoding: [0x83,0xff,0xa3,0xbf]
+0x83,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_vm_vsrc(1) ; encoding: [0x87,0xff,0xa3,0xbf]
+0x87,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_vm_vsrc(6) ; encoding: [0x9b,0xff,0xa3,0xbf]
+0x9b,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_hold_cnt(0) depctr_sa_sdst(0) depctr_va_vdst(0) depctr_va_sdst(0) depctr_va_ssrc(0) depctr_va_vcc(0) depctr_vm_vsrc(0) ; encoding: [0x00,0x00,0xa3,0xbf]
+0x00,0x00,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_hold_cnt(1) depctr_sa_sdst(1) depctr_va_vdst(15) depctr_va_sdst(7) depctr_va_ssrc(1) depctr_va_vcc(1) depctr_vm_vsrc(7) ; encoding: [0x9f,0xff,0xa3,0xbf]
+0x9f,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vdst(1) depctr_va_sdst(1) depctr_vm_vsrc(1) ; encoding: [0x87,0x13,0xa3,0xbf]
+0x87,0x13,0xa3,0xbf
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
index 7ba35e0ba50f8..66217ebe99313 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
@@ -18941,12 +18941,6 @@
# GFX10: s_wait_idle ; encoding: [0x00,0x00,0xa2,0xbf]
0x00,0x00,0xa2,0xbf
-# GFX10: s_waitcnt_depctr 0x0 ; encoding: [0x00,0x00,0xa3,0xbf]
-0x00,0x00,0xa3,0xbf
-
-# GFX10: s_waitcnt_depctr 0xfffe ; encoding: [0xfe,0xff,0xa3,0xbf]
-0xfe,0xff,0xa3,0xbf
-
# GFX10: s_wakeup ; encoding: [0x00,0x00,0x83,0xbf]
0x00,0x00,0x83,0xbf
@@ -98756,3 +98750,64 @@
# GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x div:2 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x18]
0x05 0x00 0x02 0xd6 0x00 0x00 0x00 0x18
+
+#===------------------------------------------------------------------------===#
+# s_waitcnt_depctr.
+#===------------------------------------------------------------------------===#
+
+# GFX10: s_waitcnt_depctr 0x20 ; encoding: [0x20,0x00,0xa3,0xbf]
+0x20,0x00,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr 0x40 ; encoding: [0x40,0x00,0xa3,0xbf]
+0x40,0x00,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr 0x60 ; encoding: [0x60,0x00,0xa3,0xbf]
+0x60,0x00,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr 0x80 ; encoding: [0x80,0x00,0xa3,0xbf]
+0x80,0x00,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr 0xffff ; encoding: [0xff,0xff,0xa3,0xbf]
+0xff,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_sa_sdst(0) ; encoding: [0x1e,0xff,0xa3,0xbf]
+0x1e,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vdst(0) ; encoding: [0x1f,0x0f,0xa3,0xbf]
+0x1f,0x0f,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vdst(1) ; encoding: [0x1f,0x1f,0xa3,0xbf]
+0x1f,0x1f,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vdst(14) ; encoding: [0x1f,0xef,0xa3,0xbf]
+0x1f,0xef,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_sdst(0) ; encoding: [0x1f,0xf1,0xa3,0xbf]
+0x1f,0xf1,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_sdst(6) ; encoding: [0x1f,0xfd,0xa3,0xbf]
+0x1f,0xfd,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_ssrc(0) ; encoding: [0x1f,0xfe,0xa3,0xbf]
+0x1f,0xfe,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vcc(0) ; encoding: [0x1d,0xff,0xa3,0xbf]
+0x1d,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_vm_vsrc(0) ; encoding: [0x03,0xff,0xa3,0xbf]
+0x03,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_vm_vsrc(1) ; encoding: [0x07,0xff,0xa3,0xbf]
+0x07,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_vm_vsrc(6) ; encoding: [0x1b,0xff,0xa3,0xbf]
+0x1b,0xff,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_sa_sdst(0) depctr_va_vdst(0) depctr_va_sdst(0) depctr_va_ssrc(0) depctr_va_vcc(0) depctr_vm_vsrc(0) ; encoding: [0x00,0x00,0xa3,0xbf]
+0x00,0x00,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vdst(1) depctr_va_sdst(1) depctr_vm_vsrc(1) ; encoding: [0x07,0x13,0xa3,0xbf]
+0x07,0x13,0xa3,0xbf
+
+# GFX10: s_waitcnt_depctr depctr_va_vdst(14) depctr_va_sdst(6) depctr_vm_vsrc(6) ; encoding: [0x1b,0xed,0xa3,0xbf]
+0x1b,0xed,0xa3,0xbf
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