[llvm] cde66d5 - [InstCombine] Regenerate and(srem(X,Pow2),C) test and add vector coverage

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-04-07T14:58:50+01:00
New Revision: cde66d5ed1dbc76e411da94a5220ff2af8eade79

URL: https://github.com/llvm/llvm-project/commit/cde66d5ed1dbc76e411da94a5220ff2af8eade79
DIFF: https://github.com/llvm/llvm-project/commit/cde66d5ed1dbc76e411da94a5220ff2af8eade79.diff

LOG: [InstCombine] Regenerate and(srem(X,Pow2),C) test and add vector coverage

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/2008-07-11-RemAnd.ll

Removed: 
    


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diff  --git a/llvm/test/Transforms/InstCombine/2008-07-11-RemAnd.ll b/llvm/test/Transforms/InstCombine/2008-07-11-RemAnd.ll
index 04fea07ddaf6f..67c489c054d01 100644
--- a/llvm/test/Transforms/InstCombine/2008-07-11-RemAnd.ll
+++ b/llvm/test/Transforms/InstCombine/2008-07-11-RemAnd.ll
@@ -1,9 +1,28 @@
-; RUN: opt < %s -passes=instcombine -S | not grep rem
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
 ; PR2330
 
 define i32 @a(i32 %b) nounwind  {
+; CHECK-LABEL: @a(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = and i32 [[B:%.*]], 1
+; CHECK-NEXT:    ret i32 [[TMP0]]
+;
 entry:
-	srem i32 %b, 8		; <i32>:0 [#uses=1]
-	and i32 %0, 1		; <i32>:1 [#uses=1]
-	ret i32 %1
+  srem i32 %b, 8		; <i32>:0 [#uses=1]
+  and i32 %0, 1		; <i32>:1 [#uses=1]
+  ret i32 %1
+}
+
+define <2 x i32> @a_vec(<2 x i32> %b) nounwind  {
+; CHECK-LABEL: @a_vec(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = srem <2 x i32> [[B:%.*]], <i32 8, i32 8>
+; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i32> [[TMP0]], <i32 1, i32 1>
+; CHECK-NEXT:    ret <2 x i32> [[TMP1]]
+;
+entry:
+  srem <2 x i32> %b, <i32 8, i32 8>
+  and <2 x i32> %0, <i32 1, i32 1>
+  ret <2 x i32> %1
 }