[PATCH] D122644: [RISCV] Add CMOV isel pattern for (select (setgt X, Imm), Y, Z)

[LiqinWeng via Phabricator via llvm-commits]

Miss_Grape added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/select-cc.ll:124
 ; RV32IBT-NEXT:    lw a1, 0(a1)
-; RV32IBT-NEXT:    slti a3, a2, 1
-; RV32IBT-NEXT:    cmov a0, a3, a0, a2
-; RV32IBT-NEXT:    sltz a2, a2
-; RV32IBT-NEXT:    cmov a0, a2, a1, a0
+; RV32IBT-NEXT:    slt a3, a2, a4
+; RV32IBT-NEXT:    cmov a0, a3, a0, a4
----------------
craig.topper wrote:
> This doesn't look like it's doing what it was supposed to do. The immediate is in a register.
1024 used twice， whicn used sgt and ugt. I changed the immediate value of ugt to 2046


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122644/new/

https://reviews.llvm.org/D122644