[llvm] 9d45344 - [RISCV][NFC] Remove '--check-prefixes=CHECK' in some cases as they are default
Ben Shi via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 5 20:22:37 PDT 2022
Author: Ping Deng
Date: 2022-04-06T03:18:01Z
New Revision: 9d453446facb03fa4763a309ddaf0f7ebf1c1e53
URL: https://github.com/llvm/llvm-project/commit/9d453446facb03fa4763a309ddaf0f7ebf1c1e53
DIFF: https://github.com/llvm/llvm-project/commit/9d453446facb03fa4763a309ddaf0f7ebf1c1e53.diff
LOG: [RISCV][NFC] Remove '--check-prefixes=CHECK' in some cases as they are default
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D122961
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccsu.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccus.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vwmacc-sdnode.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll
index eac549342c2f0..7de616aea9cf8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
-; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
define <2 x i16> @vwmacc_v2i16(<2 x i8>* %x, <2 x i8>* %y, <2 x i16> %z) {
; CHECK-LABEL: vwmacc_v2i16:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccsu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccsu.ll
index 35b0a4b9961ba..b5345bc7eb2a5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccsu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccsu.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
-; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
define <2 x i16> @vwmaccsu_v2i16(<2 x i8>* %x, <2 x i8>* %y, <2 x i16> %z) {
; CHECK-LABEL: vwmaccsu_v2i16:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll
index b3e9663b8acb7..b07eade29fcec 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
-; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
define <2 x i16> @vwmaccu_v2i16(<2 x i8>* %x, <2 x i8>* %y, <2 x i16> %z) {
; CHECK-LABEL: vwmaccu_v2i16:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccus.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccus.ll
index 9edc2cb83fb0e..358e7ff9b50b1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccus.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccus.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
-; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
define <2 x i16> @vwmaccus_vx_v2i16(<2 x i8>* %x, i8 %y, <2 x i16> %z) {
; CHECK-LABEL: vwmaccus_vx_v2i16:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
index 1351adec9523e..fd05f10311921 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
-; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
define <2 x i16> @vwmulu_v2i16(<2 x i8>* %x, <2 x i8>* %y) {
; CHECK-LABEL: vwmulu_v2i16:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
index 800fa67ca08bb..7a86223747849 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @vfptrunc_nxv1f32_nxv1f16(<vscale x 1 x float> %va) {
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll
index 47d04a80573b4..ad504c4c16146 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i32> @vnsra_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vnsra_wv_nxv1i32_sext:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll
index 70141889e10ab..80e078f0b824a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i32> @vnsrl_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vnsrl_wv_nxv1i32_sext:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmacc-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwmacc-sdnode.ll
index 4911ae20d3c39..2e373799ffe50 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwmacc-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwmacc-sdnode.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i64> @vwmacc_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i64> %vc) {
; CHECK-LABEL: vwmacc_vv_nxv1i32:
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