[llvm] a3d5102 - [RISCV] [NFC] Add Immediate tests for the cmov instruction
Ben Shi via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 5 20:09:11 PDT 2022
Author: Liqin Weng
Date: 2022-04-06T03:08:55Z
New Revision: a3d510220f7b1795c23773a67b153f8f8f93e8ac
URL: https://github.com/llvm/llvm-project/commit/a3d510220f7b1795c23773a67b153f8f8f93e8ac
DIFF: https://github.com/llvm/llvm-project/commit/a3d510220f7b1795c23773a67b153f8f8f93e8ac.diff
LOG: [RISCV] [NFC] Add Immediate tests for the cmov instruction
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D122723
Added:
Modified:
llvm/test/CodeGen/RISCV/i64-icmp.ll
llvm/test/CodeGen/RISCV/rv32zbt.ll
llvm/test/CodeGen/RISCV/rv64zbt.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/i64-icmp.ll b/llvm/test/CodeGen/RISCV/i64-icmp.ll
index cbd1d6a9a008e..db8404b03d2a2 100644
--- a/llvm/test/CodeGen/RISCV/i64-icmp.ll
+++ b/llvm/test/CodeGen/RISCV/i64-icmp.ll
@@ -205,13 +205,11 @@ define i64 @icmp_ugt_constant_2046(i64 %a) nounwind {
define i64 @icmp_ugt_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_ugt_constant_neg_2049:
; RV64I: # %bb.0:
-; RV64I-NEXT: lui a1, 1046527
-; RV64I-NEXT: slli a1, a1, 20
-; RV64I-NEXT: srli a1, a1, 32
-; RV64I-NEXT: sltu a0, a1, a0
+; RV64I-NEXT: sltiu a0, a0, -2048
+; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
-; 4294965247 signed extend is -2049
- %1 = icmp ugt i64 %a, 4294965247
+; 18446744073709549567 signed extend is -2049
+ %1 = icmp ugt i64 %a, 18446744073709549567
%2 = zext i1 %1 to i64
ret i64 %2
}
@@ -219,13 +217,12 @@ define i64 @icmp_ugt_constant_neg_2049(i64 %a) nounwind {
define i64 @icmp_ugt_constant_neg_2050(i64 %a) nounwind {
; RV64I-LABEL: icmp_ugt_constant_neg_2050:
; RV64I: # %bb.0:
-; RV64I-NEXT: li a1, -1025
-; RV64I-NEXT: slli a1, a1, 33
-; RV64I-NEXT: srli a1, a1, 32
+; RV64I-NEXT: lui a1, 1048575
+; RV64I-NEXT: addiw a1, a1, 2046
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: ret
-; 4294965246 signed extend is -2050
- %1 = icmp ugt i64 %a, 4294965246
+; 18446744073709549566 signed extend is -2050
+ %1 = icmp ugt i64 %a, 18446744073709549566
%2 = zext i1 %1 to i64
ret i64 %2
}
@@ -276,13 +273,11 @@ define i64 @icmp_uge_constant_2048(i64 %a) nounwind {
define i64 @icmp_uge_constant_neg_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_uge_constant_neg_2048:
; RV64I: # %bb.0:
-; RV64I-NEXT: lui a1, 1046527
-; RV64I-NEXT: slli a1, a1, 20
-; RV64I-NEXT: srli a1, a1, 32
-; RV64I-NEXT: sltu a0, a1, a0
+; RV64I-NEXT: sltiu a0, a0, -2048
+; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
-; 4294965248 signed extend is -2048
- %1 = icmp uge i64 %a, 4294965248
+; 18446744073709549568 signed extend is -2048
+ %1 = icmp uge i64 %a, 18446744073709549568
%2 = zext i1 %1 to i64
ret i64 %2
}
@@ -290,13 +285,12 @@ define i64 @icmp_uge_constant_neg_2048(i64 %a) nounwind {
define i64 @icmp_uge_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_uge_constant_neg_2049:
; RV64I: # %bb.0:
-; RV64I-NEXT: li a1, -1025
-; RV64I-NEXT: slli a1, a1, 33
-; RV64I-NEXT: srli a1, a1, 32
+; RV64I-NEXT: lui a1, 1048575
+; RV64I-NEXT: addiw a1, a1, 2046
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: ret
-; 4294965247 signed extend is -2049
- %1 = icmp uge i64 %a, 4294965247
+; 18446744073709549567 signed extend is -2049
+ %1 = icmp uge i64 %a, 18446744073709549567
%2 = zext i1 %1 to i64
ret i64 %2
}
@@ -345,13 +339,10 @@ define i64 @icmp_ult_constant_2048(i64 %a) nounwind {
define i64 @icmp_ult_constant_neg_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_ult_constant_neg_2048:
; RV64I: # %bb.0:
-; RV64I-NEXT: li a1, 1
-; RV64I-NEXT: slli a1, a1, 32
-; RV64I-NEXT: addi a1, a1, -2048
-; RV64I-NEXT: sltu a0, a0, a1
+; RV64I-NEXT: sltiu a0, a0, -2048
; RV64I-NEXT: ret
-; 4294965248 signed extend is -2048
- %1 = icmp ult i64 %a, 4294965248
+; 18446744073709549568 signed extend is -2048
+ %1 = icmp ult i64 %a, 18446744073709549568
%2 = zext i1 %1 to i64
ret i64 %2
}
@@ -359,13 +350,12 @@ define i64 @icmp_ult_constant_neg_2048(i64 %a) nounwind {
define i64 @icmp_ult_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_ult_constant_neg_2049:
; RV64I: # %bb.0:
-; RV64I-NEXT: lui a1, 1046527
-; RV64I-NEXT: slli a1, a1, 20
-; RV64I-NEXT: srli a1, a1, 32
+; RV64I-NEXT: lui a1, 1048575
+; RV64I-NEXT: addiw a1, a1, 2047
; RV64I-NEXT: sltu a0, a0, a1
; RV64I-NEXT: ret
-; 4294965247 signed extend is -2049
- %1 = icmp ult i64 %a, 4294965247
+; 18446744073709549567 signed extend is -2049
+ %1 = icmp ult i64 %a, 18446744073709549567
%2 = zext i1 %1 to i64
ret i64 %2
}
@@ -415,13 +405,10 @@ define i64 @icmp_ule_constant_2047(i64 %a) nounwind {
define i64 @icmp_ule_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_ule_constant_neg_2049:
; RV64I: # %bb.0:
-; RV64I-NEXT: li a1, 1
-; RV64I-NEXT: slli a1, a1, 32
-; RV64I-NEXT: addi a1, a1, -2048
-; RV64I-NEXT: sltu a0, a0, a1
+; RV64I-NEXT: sltiu a0, a0, -2048
; RV64I-NEXT: ret
-; 4294965247 signed extend is -2049
- %1 = icmp ule i64 %a, 4294965247
+; 18446744073709549567 signed extend is -2049
+ %1 = icmp ule i64 %a, 18446744073709549567
%2 = zext i1 %1 to i64
ret i64 %2
}
@@ -429,13 +416,12 @@ define i64 @icmp_ule_constant_neg_2049(i64 %a) nounwind {
define i64 @icmp_ule_constant_neg_2050(i64 %a) nounwind {
; RV64I-LABEL: icmp_ule_constant_neg_2050:
; RV64I: # %bb.0:
-; RV64I-NEXT: lui a1, 1046527
-; RV64I-NEXT: slli a1, a1, 20
-; RV64I-NEXT: srli a1, a1, 32
+; RV64I-NEXT: lui a1, 1048575
+; RV64I-NEXT: addiw a1, a1, 2047
; RV64I-NEXT: sltu a0, a0, a1
; RV64I-NEXT: ret
-; 4294965246 signed extend is -2050
- %1 = icmp ule i64 %a, 4294965246
+; 18446744073709549566 signed extend is -2050
+ %1 = icmp ule i64 %a, 18446744073709549566
%2 = zext i1 %1 to i64
ret i64 %2
}
diff --git a/llvm/test/CodeGen/RISCV/rv32zbt.ll b/llvm/test/CodeGen/RISCV/rv32zbt.ll
index 7500e07c59754..f3dd2a99f5799 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbt.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbt.ll
@@ -89,32 +89,169 @@ define i64 @cmix_i64_2(i64 %a, i64 %b, i64 %c) nounwind {
ret i64 %xor1
}
-define i32 @cmov_i32(i32 %a, i32 %b, i32 %c) nounwind {
-; RV32I-LABEL: cmov_i32:
+define i32 @cmov_eq_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
+; RV32I-LABEL: cmov_eq_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: beqz a1, .LBB4_2
+; RV32I-NEXT: beq a1, a2, .LBB4_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB4_2:
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: cmov_eq_i32:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: xor a1, a1, a2
+; RV32ZBT-NEXT: cmov a0, a1, a3, a0
+; RV32ZBT-NEXT: ret
+ %tobool.not = icmp eq i32 %b, %c
+ %cond = select i1 %tobool.not, i32 %a, i32 %d
+ ret i32 %cond
+}
+
+define i32 @cmov_eq_i32_constant_zero(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_eq_i32_constant_zero:
+; RV32I: # %bb.0:
+; RV32I-NEXT: beqz a1, .LBB5_2
+; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: .LBB5_2:
; RV32I-NEXT: ret
;
-; RV32ZBT-LABEL: cmov_i32:
+; RV32ZBT-LABEL: cmov_eq_i32_constant_zero:
; RV32ZBT: # %bb.0:
-; RV32ZBT-NEXT: cmov a0, a1, a0, a2
+; RV32ZBT-NEXT: cmov a0, a1, a2, a0
; RV32ZBT-NEXT: ret
%tobool.not = icmp eq i32 %b, 0
- %cond = select i1 %tobool.not, i32 %c, i32 %a
+ %cond = select i1 %tobool.not, i32 %a, i32 %c
+ ret i32 %cond
+}
+
+define i32 @cmov_eq_i32_constant_2048(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_eq_i32_constant_2048:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a3, 1
+; RV32I-NEXT: addi a3, a3, -2048
+; RV32I-NEXT: beq a1, a3, .LBB6_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: .LBB6_2:
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: cmov_eq_i32_constant_2048:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: addi a1, a1, -2048
+; RV32ZBT-NEXT: cmov a0, a1, a2, a0
+; RV32ZBT-NEXT: ret
+ %tobool.not = icmp eq i32 %b, 2048
+ %cond = select i1 %tobool.not, i32 %a, i32 %c
+ ret i32 %cond
+}
+
+define i32 @cmov_eq_i32_constant_neg_2047(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_eq_i32_constant_neg_2047:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a3, -2047
+; RV32I-NEXT: beq a1, a3, .LBB7_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: .LBB7_2:
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: cmov_eq_i32_constant_neg_2047:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: addi a1, a1, 2047
+; RV32ZBT-NEXT: cmov a0, a1, a2, a0
+; RV32ZBT-NEXT: ret
+ %tobool.not = icmp eq i32 %b, -2047
+ %cond = select i1 %tobool.not, i32 %a, i32 %c
+ ret i32 %cond
+}
+
+define i32 @cmov_ne_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
+; RV32I-LABEL: cmov_ne_i32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: bne a1, a2, .LBB8_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB8_2:
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: cmov_ne_i32:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: xor a1, a1, a2
+; RV32ZBT-NEXT: cmov a0, a1, a0, a3
+; RV32ZBT-NEXT: ret
+ %tobool.not = icmp ne i32 %b, %c
+ %cond = select i1 %tobool.not, i32 %a, i32 %d
+ ret i32 %cond
+}
+
+define i32 @cmov_ne_i32_constant_zero(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_ne_i32_constant_zero:
+; RV32I: # %bb.0:
+; RV32I-NEXT: bnez a1, .LBB9_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: .LBB9_2:
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: cmov_ne_i32_constant_zero:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: cmov a0, a1, a0, a2
+; RV32ZBT-NEXT: ret
+ %tobool.not = icmp ne i32 %b, 0
+ %cond = select i1 %tobool.not, i32 %a, i32 %c
+ ret i32 %cond
+}
+
+define i32 @cmov_ne_i32_constant_2048(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_ne_i32_constant_2048:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a3, 1
+; RV32I-NEXT: addi a3, a3, -2048
+; RV32I-NEXT: bne a1, a3, .LBB10_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: .LBB10_2:
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: cmov_ne_i32_constant_2048:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: addi a1, a1, -2048
+; RV32ZBT-NEXT: cmov a0, a1, a0, a2
+; RV32ZBT-NEXT: ret
+ %tobool.not = icmp ne i32 %b, 2048
+ %cond = select i1 %tobool.not, i32 %a, i32 %c
+ ret i32 %cond
+}
+
+define i32 @cmov_ne_i32_constant_neg_2047(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_ne_i32_constant_neg_2047:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a3, -2047
+; RV32I-NEXT: bne a1, a3, .LBB11_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: .LBB11_2:
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: cmov_ne_i32_constant_neg_2047:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: addi a1, a1, 2047
+; RV32ZBT-NEXT: cmov a0, a1, a0, a2
+; RV32ZBT-NEXT: ret
+ %tobool.not = icmp ne i32 %b, -2047
+ %cond = select i1 %tobool.not, i32 %a, i32 %c
ret i32 %cond
}
define i32 @cmov_sle_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_sle_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: bge a2, a1, .LBB5_2
+; RV32I-NEXT: bge a2, a1, .LBB12_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: .LBB5_2:
+; RV32I-NEXT: .LBB12_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_sle_i32:
@@ -127,13 +264,115 @@ define i32 @cmov_sle_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
ret i32 %cond
}
+define i32 @cmov_sle_i32_constant_2046(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_sle_i32_constant_2046:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a3, 2047
+; RV32I-NEXT: blt a1, a3, .LBB13_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: .LBB13_2:
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: cmov_sle_i32_constant_2046:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: slti a1, a1, 2047
+; RV32ZBT-NEXT: cmov a0, a1, a0, a2
+; RV32ZBT-NEXT: ret
+ %tobool = icmp sle i32 %b, 2046
+ %cond = select i1 %tobool, i32 %a, i32 %c
+ ret i32 %cond
+}
+
+define i32 @cmov_sle_i32_constant_neg_2049(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_sle_i32_constant_neg_2049:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a3, -2048
+; RV32I-NEXT: blt a1, a3, .LBB14_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: .LBB14_2:
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: cmov_sle_i32_constant_neg_2049:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: slti a1, a1, -2048
+; RV32ZBT-NEXT: cmov a0, a1, a0, a2
+; RV32ZBT-NEXT: ret
+ %tobool = icmp sle i32 %b, -2049
+ %cond = select i1 %tobool, i32 %a, i32 %c
+ ret i32 %cond
+}
+
+define i32 @cmov_sgt_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
+; RV32I-LABEL: cmov_sgt_i32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: blt a2, a1, .LBB15_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB15_2:
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: cmov_sgt_i32:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: slt a1, a2, a1
+; RV32ZBT-NEXT: cmov a0, a1, a0, a3
+; RV32ZBT-NEXT: ret
+ %tobool = icmp sgt i32 %b, %c
+ %cond = select i1 %tobool, i32 %a, i32 %d
+ ret i32 %cond
+}
+
+define i32 @cmov_sgt_i32_constant_2046(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_sgt_i32_constant_2046:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a3, 2046
+; RV32I-NEXT: blt a3, a1, .LBB16_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: .LBB16_2:
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: cmov_sgt_i32_constant_2046:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: slti a1, a1, 2047
+; RV32ZBT-NEXT: xori a1, a1, 1
+; RV32ZBT-NEXT: cmov a0, a1, a0, a2
+; RV32ZBT-NEXT: ret
+ %tobool = icmp sgt i32 %b, 2046
+ %cond = select i1 %tobool, i32 %a, i32 %c
+ ret i32 %cond
+}
+
+define i32 @cmov_sgt_i32_constant_neg_2049(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_sgt_i32_constant_neg_2049:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a3, 1048575
+; RV32I-NEXT: addi a3, a3, 2047
+; RV32I-NEXT: blt a3, a1, .LBB17_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: .LBB17_2:
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: cmov_sgt_i32_constant_neg_2049:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: slti a1, a1, -2048
+; RV32ZBT-NEXT: xori a1, a1, 1
+; RV32ZBT-NEXT: cmov a0, a1, a0, a2
+; RV32ZBT-NEXT: ret
+ %tobool = icmp sgt i32 %b, -2049
+ %cond = select i1 %tobool, i32 %a, i32 %c
+ ret i32 %cond
+}
+
define i32 @cmov_sge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_sge_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: bge a1, a2, .LBB6_2
+; RV32I-NEXT: bge a1, a2, .LBB18_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: .LBB6_2:
+; RV32I-NEXT: .LBB18_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_sge_i32:
@@ -146,13 +385,56 @@ define i32 @cmov_sge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
ret i32 %cond
}
+define i32 @cmov_sge_i32_constant_2047(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_sge_i32_constant_2047:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a3, 2046
+; RV32I-NEXT: blt a3, a1, .LBB19_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: .LBB19_2:
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: cmov_sge_i32_constant_2047:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: slti a1, a1, 2047
+; RV32ZBT-NEXT: xori a1, a1, 1
+; RV32ZBT-NEXT: cmov a0, a1, a0, a2
+; RV32ZBT-NEXT: ret
+ %tobool = icmp sge i32 %b, 2047
+ %cond = select i1 %tobool, i32 %a, i32 %c
+ ret i32 %cond
+}
+
+define i32 @cmov_sge_i32_constant_neg_2048(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_sge_i32_constant_neg_2048:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a3, 1048575
+; RV32I-NEXT: addi a3, a3, 2047
+; RV32I-NEXT: blt a3, a1, .LBB20_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: .LBB20_2:
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: cmov_sge_i32_constant_neg_2048:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: slti a1, a1, -2048
+; RV32ZBT-NEXT: xori a1, a1, 1
+; RV32ZBT-NEXT: cmov a0, a1, a0, a2
+; RV32ZBT-NEXT: ret
+ %tobool = icmp sge i32 %b, -2048
+ %cond = select i1 %tobool, i32 %a, i32 %c
+ ret i32 %cond
+}
+
define i32 @cmov_ule_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_ule_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: bgeu a2, a1, .LBB7_2
+; RV32I-NEXT: bgeu a2, a1, .LBB21_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: .LBB7_2:
+; RV32I-NEXT: .LBB21_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_ule_i32:
@@ -165,13 +447,115 @@ define i32 @cmov_ule_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
ret i32 %cond
}
+define i32 @cmov_ule_i32_constant_2047(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_ule_i32_constant_2047:
+; RV32I: # %bb.0:
+; RV32I-NEXT: srli a1, a1, 11
+; RV32I-NEXT: beqz a1, .LBB22_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: .LBB22_2:
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: cmov_ule_i32_constant_2047:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: srli a1, a1, 11
+; RV32ZBT-NEXT: cmov a0, a1, a2, a0
+; RV32ZBT-NEXT: ret
+ %tobool = icmp ule i32 %b, 2047
+ %cond = select i1 %tobool, i32 %a, i32 %c
+ ret i32 %cond
+}
+
+define i32 @cmov_ule_i32_constant_neg_2049(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_ule_i32_constant_neg_2049:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a3, -2048
+; RV32I-NEXT: bltu a1, a3, .LBB23_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: .LBB23_2:
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: cmov_ule_i32_constant_neg_2049:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: sltiu a1, a1, -2048
+; RV32ZBT-NEXT: cmov a0, a1, a0, a2
+; RV32ZBT-NEXT: ret
+ %tobool = icmp ule i32 %b, 4294965247
+ %cond = select i1 %tobool, i32 %a, i32 %c
+ ret i32 %cond
+}
+
+define i32 @cmov_ugt_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
+; RV32I-LABEL: cmov_ugt_i32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: bltu a2, a1, .LBB24_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a3
+; RV32I-NEXT: .LBB24_2:
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: cmov_ugt_i32:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: sltu a1, a2, a1
+; RV32ZBT-NEXT: cmov a0, a1, a0, a3
+; RV32ZBT-NEXT: ret
+ %tobool = icmp ugt i32 %b, %c
+ %cond = select i1 %tobool, i32 %a, i32 %d
+ ret i32 %cond
+}
+
+define i32 @cmov_ugt_i32_constant_2046(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_ugt_i32_constant_2046:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a3, 2046
+; RV32I-NEXT: bltu a3, a1, .LBB25_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: .LBB25_2:
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: cmov_ugt_i32_constant_2046:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: sltiu a1, a1, 2047
+; RV32ZBT-NEXT: xori a1, a1, 1
+; RV32ZBT-NEXT: cmov a0, a1, a0, a2
+; RV32ZBT-NEXT: ret
+ %tobool = icmp ugt i32 %b, 2046
+ %cond = select i1 %tobool, i32 %a, i32 %c
+ ret i32 %cond
+}
+
+define i32 @cmov_ugt_i32_constant_neg_2049(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_ugt_i32_constant_neg_2049:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a3, 1048575
+; RV32I-NEXT: addi a3, a3, 2047
+; RV32I-NEXT: bltu a3, a1, .LBB26_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: .LBB26_2:
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: cmov_ugt_i32_constant_neg_2049:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: sltiu a1, a1, -2048
+; RV32ZBT-NEXT: xori a1, a1, 1
+; RV32ZBT-NEXT: cmov a0, a1, a0, a2
+; RV32ZBT-NEXT: ret
+ %tobool = icmp ugt i32 %b, 4294965247
+ %cond = select i1 %tobool, i32 %a, i32 %c
+ ret i32 %cond
+}
+
define i32 @cmov_uge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_uge_i32:
; RV32I: # %bb.0:
-; RV32I-NEXT: bgeu a1, a2, .LBB8_2
+; RV32I-NEXT: bgeu a1, a2, .LBB27_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a3
-; RV32I-NEXT: .LBB8_2:
+; RV32I-NEXT: .LBB27_2:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_uge_i32:
@@ -184,15 +568,58 @@ define i32 @cmov_uge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
ret i32 %cond
}
+define i32 @cmov_uge_i32_constant_2047(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_uge_i32_constant_2047:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a3, 2046
+; RV32I-NEXT: bltu a3, a1, .LBB28_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: .LBB28_2:
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: cmov_uge_i32_constant_2047:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: sltiu a1, a1, 2047
+; RV32ZBT-NEXT: xori a1, a1, 1
+; RV32ZBT-NEXT: cmov a0, a1, a0, a2
+; RV32ZBT-NEXT: ret
+ %tobool = icmp uge i32 %b, 2047
+ %cond = select i1 %tobool, i32 %a, i32 %c
+ ret i32 %cond
+}
+
+define i32 @cmov_uge_i32_constant_neg_2048(i32 %a, i32 %b, i32 %c) nounwind {
+; RV32I-LABEL: cmov_uge_i32_constant_neg_2048:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a3, 1048575
+; RV32I-NEXT: addi a3, a3, 2047
+; RV32I-NEXT: bltu a3, a1, .LBB29_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: .LBB29_2:
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: cmov_uge_i32_constant_neg_2048:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: sltiu a1, a1, -2048
+; RV32ZBT-NEXT: xori a1, a1, 1
+; RV32ZBT-NEXT: cmov a0, a1, a0, a2
+; RV32ZBT-NEXT: ret
+ %tobool = icmp uge i32 %b, 4294965248
+ %cond = select i1 %tobool, i32 %a, i32 %c
+ ret i32 %cond
+}
+
define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: cmov_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: or a2, a2, a3
-; RV32I-NEXT: beqz a2, .LBB9_2
+; RV32I-NEXT: beqz a2, .LBB30_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: mv a5, a1
-; RV32I-NEXT: .LBB9_2:
+; RV32I-NEXT: .LBB30_2:
; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: ret
@@ -211,20 +638,20 @@ define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind {
define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV32I-LABEL: cmov_sle_i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: beq a3, a5, .LBB10_2
+; RV32I-NEXT: beq a3, a5, .LBB31_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: slt a2, a5, a3
; RV32I-NEXT: xori a2, a2, 1
-; RV32I-NEXT: beqz a2, .LBB10_3
-; RV32I-NEXT: j .LBB10_4
-; RV32I-NEXT: .LBB10_2:
+; RV32I-NEXT: beqz a2, .LBB31_3
+; RV32I-NEXT: j .LBB31_4
+; RV32I-NEXT: .LBB31_2:
; RV32I-NEXT: sltu a2, a4, a2
; RV32I-NEXT: xori a2, a2, 1
-; RV32I-NEXT: bnez a2, .LBB10_4
-; RV32I-NEXT: .LBB10_3:
+; RV32I-NEXT: bnez a2, .LBB31_4
+; RV32I-NEXT: .LBB31_3:
; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a7
-; RV32I-NEXT: .LBB10_4:
+; RV32I-NEXT: .LBB31_4:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_sle_i64:
@@ -246,20 +673,20 @@ define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV32I-LABEL: cmov_sge_i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: beq a3, a5, .LBB11_2
+; RV32I-NEXT: beq a3, a5, .LBB32_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: slt a2, a3, a5
; RV32I-NEXT: xori a2, a2, 1
-; RV32I-NEXT: beqz a2, .LBB11_3
-; RV32I-NEXT: j .LBB11_4
-; RV32I-NEXT: .LBB11_2:
+; RV32I-NEXT: beqz a2, .LBB32_3
+; RV32I-NEXT: j .LBB32_4
+; RV32I-NEXT: .LBB32_2:
; RV32I-NEXT: sltu a2, a2, a4
; RV32I-NEXT: xori a2, a2, 1
-; RV32I-NEXT: bnez a2, .LBB11_4
-; RV32I-NEXT: .LBB11_3:
+; RV32I-NEXT: bnez a2, .LBB32_4
+; RV32I-NEXT: .LBB32_3:
; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a7
-; RV32I-NEXT: .LBB11_4:
+; RV32I-NEXT: .LBB32_4:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_sge_i64:
@@ -281,20 +708,20 @@ define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV32I-LABEL: cmov_ule_i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: beq a3, a5, .LBB12_2
+; RV32I-NEXT: beq a3, a5, .LBB33_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a2, a5, a3
; RV32I-NEXT: xori a2, a2, 1
-; RV32I-NEXT: beqz a2, .LBB12_3
-; RV32I-NEXT: j .LBB12_4
-; RV32I-NEXT: .LBB12_2:
+; RV32I-NEXT: beqz a2, .LBB33_3
+; RV32I-NEXT: j .LBB33_4
+; RV32I-NEXT: .LBB33_2:
; RV32I-NEXT: sltu a2, a4, a2
; RV32I-NEXT: xori a2, a2, 1
-; RV32I-NEXT: bnez a2, .LBB12_4
-; RV32I-NEXT: .LBB12_3:
+; RV32I-NEXT: bnez a2, .LBB33_4
+; RV32I-NEXT: .LBB33_3:
; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a7
-; RV32I-NEXT: .LBB12_4:
+; RV32I-NEXT: .LBB33_4:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_ule_i64:
@@ -316,20 +743,20 @@ define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV32I-LABEL: cmov_uge_i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: beq a3, a5, .LBB13_2
+; RV32I-NEXT: beq a3, a5, .LBB34_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a2, a3, a5
; RV32I-NEXT: xori a2, a2, 1
-; RV32I-NEXT: beqz a2, .LBB13_3
-; RV32I-NEXT: j .LBB13_4
-; RV32I-NEXT: .LBB13_2:
+; RV32I-NEXT: beqz a2, .LBB34_3
+; RV32I-NEXT: j .LBB34_4
+; RV32I-NEXT: .LBB34_2:
; RV32I-NEXT: sltu a2, a2, a4
; RV32I-NEXT: xori a2, a2, 1
-; RV32I-NEXT: bnez a2, .LBB13_4
-; RV32I-NEXT: .LBB13_3:
+; RV32I-NEXT: bnez a2, .LBB34_4
+; RV32I-NEXT: .LBB34_3:
; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a7
-; RV32I-NEXT: .LBB13_4:
+; RV32I-NEXT: .LBB34_4:
; RV32I-NEXT: ret
;
; RV32ZBT-LABEL: cmov_uge_i64:
@@ -383,23 +810,23 @@ define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV32I-NEXT: srli a5, a4, 5
; RV32I-NEXT: andi a6, a5, 1
; RV32I-NEXT: mv a5, a3
-; RV32I-NEXT: bnez a6, .LBB15_2
+; RV32I-NEXT: bnez a6, .LBB36_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a5, a0
-; RV32I-NEXT: .LBB15_2:
+; RV32I-NEXT: .LBB36_2:
; RV32I-NEXT: sll a7, a5, a4
-; RV32I-NEXT: bnez a6, .LBB15_4
+; RV32I-NEXT: bnez a6, .LBB36_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: mv a2, a3
-; RV32I-NEXT: .LBB15_4:
+; RV32I-NEXT: .LBB36_4:
; RV32I-NEXT: srli a2, a2, 1
; RV32I-NEXT: not a3, a4
; RV32I-NEXT: srl a2, a2, a3
; RV32I-NEXT: or a2, a7, a2
-; RV32I-NEXT: bnez a6, .LBB15_6
+; RV32I-NEXT: bnez a6, .LBB36_6
; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: .LBB15_6:
+; RV32I-NEXT: .LBB36_6:
; RV32I-NEXT: sll a0, a0, a4
; RV32I-NEXT: srli a1, a5, 1
; RV32I-NEXT: srl a1, a1, a3
@@ -456,24 +883,24 @@ define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: fshr_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a5, a4, 32
-; RV32I-NEXT: beqz a5, .LBB17_2
+; RV32I-NEXT: beqz a5, .LBB38_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a2, a3
-; RV32I-NEXT: .LBB17_2:
+; RV32I-NEXT: .LBB38_2:
; RV32I-NEXT: srl a2, a2, a4
-; RV32I-NEXT: beqz a5, .LBB17_4
+; RV32I-NEXT: beqz a5, .LBB38_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: mv a3, a0
-; RV32I-NEXT: .LBB17_4:
+; RV32I-NEXT: .LBB38_4:
; RV32I-NEXT: slli a7, a3, 1
; RV32I-NEXT: not a6, a4
; RV32I-NEXT: sll a7, a7, a6
; RV32I-NEXT: or a2, a7, a2
; RV32I-NEXT: srl a3, a3, a4
-; RV32I-NEXT: beqz a5, .LBB17_6
+; RV32I-NEXT: beqz a5, .LBB38_6
; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: .LBB17_6:
+; RV32I-NEXT: .LBB38_6:
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: sll a0, a0, a6
; RV32I-NEXT: or a1, a0, a3
@@ -570,3 +997,4 @@ define i64 @fshli_i64(i64 %a, i64 %b) nounwind {
%1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 5)
ret i64 %1
}
+
diff --git a/llvm/test/CodeGen/RISCV/rv64zbt.ll b/llvm/test/CodeGen/RISCV/rv64zbt.ll
index 28a7db360e6fc..d93ff40acc168 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbt.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbt.ll
@@ -194,13 +194,132 @@ define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind {
ret i64 %cond
}
+define i64 @cmov_eq_i64_constant_2048(i64 %a, i64 %b, i64 %c) nounwind {
+; RV64I-LABEL: cmov_eq_i64_constant_2048:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a3, 1
+; RV64I-NEXT: addiw a3, a3, -2048
+; RV64I-NEXT: beq a1, a3, .LBB10_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB10_2:
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: cmov_eq_i64_constant_2048:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: addi a1, a1, -2048
+; RV64ZBT-NEXT: cmov a0, a1, a2, a0
+; RV64ZBT-NEXT: ret
+ %tobool.not = icmp eq i64 %b, 2048
+ %cond = select i1 %tobool.not, i64 %a, i64 %c
+ ret i64 %cond
+}
+
+define i64 @cmov_eq_i64_constant_neg_2047(i64 %a, i64 %b, i64 %c) nounwind {
+; RV64I-LABEL: cmov_eq_i64_constant_neg_2047:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a3, -2047
+; RV64I-NEXT: beq a1, a3, .LBB11_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB11_2:
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: cmov_eq_i64_constant_neg_2047:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: addi a1, a1, 2047
+; RV64ZBT-NEXT: cmov a0, a1, a2, a0
+; RV64ZBT-NEXT: ret
+ %tobool.not = icmp eq i64 %b, -2047
+ %cond = select i1 %tobool.not, i64 %a, i64 %c
+ ret i64 %cond
+}
+
+define i64 @cmov_ne_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
+; RV64I-LABEL: cmov_ne_i64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: bne a1, a2, .LBB12_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a3
+; RV64I-NEXT: .LBB12_2:
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: cmov_ne_i64:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: xor a1, a1, a2
+; RV64ZBT-NEXT: cmov a0, a1, a0, a3
+; RV64ZBT-NEXT: ret
+ %tobool.not = icmp ne i64 %b, %c
+ %cond = select i1 %tobool.not, i64 %a, i64 %d
+ ret i64 %cond
+}
+
+define i64 @cmov_ne_i64_constant_zero(i64 %a, i64 %b, i64 %c) nounwind {
+; RV64I-LABEL: cmov_ne_i64_constant_zero:
+; RV64I: # %bb.0:
+; RV64I-NEXT: bnez a1, .LBB13_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB13_2:
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: cmov_ne_i64_constant_zero:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: cmov a0, a1, a0, a2
+; RV64ZBT-NEXT: ret
+ %tobool.not = icmp ne i64 %b, 0
+ %cond = select i1 %tobool.not, i64 %a, i64 %c
+ ret i64 %cond
+}
+
+define i64 @cmov_ne_i64_constant_2048(i64 %a, i64 %b, i64 %c) nounwind {
+; RV64I-LABEL: cmov_ne_i64_constant_2048:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a3, 1
+; RV64I-NEXT: addiw a3, a3, -2048
+; RV64I-NEXT: bne a1, a3, .LBB14_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB14_2:
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: cmov_ne_i64_constant_2048:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: addi a1, a1, -2048
+; RV64ZBT-NEXT: cmov a0, a1, a0, a2
+; RV64ZBT-NEXT: ret
+ %tobool.not = icmp ne i64 %b, 2048
+ %cond = select i1 %tobool.not, i64 %a, i64 %c
+ ret i64 %cond
+}
+
+define i64 @cmov_ne_i64_constant_neg_2047(i64 %a, i64 %b, i64 %c) nounwind {
+; RV64I-LABEL: cmov_ne_i64_constant_neg_2047:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a3, -2047
+; RV64I-NEXT: bne a1, a3, .LBB15_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB15_2:
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: cmov_ne_i64_constant_neg_2047:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: addi a1, a1, 2047
+; RV64ZBT-NEXT: cmov a0, a1, a0, a2
+; RV64ZBT-NEXT: ret
+ %tobool.not = icmp ne i64 %b, -2047
+ %cond = select i1 %tobool.not, i64 %a, i64 %c
+ ret i64 %cond
+}
+
define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_sle_i64:
; RV64I: # %bb.0:
-; RV64I-NEXT: bge a2, a1, .LBB10_2
+; RV64I-NEXT: bge a2, a1, .LBB16_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: .LBB10_2:
+; RV64I-NEXT: .LBB16_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_sle_i64:
@@ -213,13 +332,115 @@ define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
ret i64 %cond
}
+define i64 @cmov_sle_i64_constant_2046(i64 %a, i64 %b, i64 %c) nounwind {
+; RV64I-LABEL: cmov_sle_i64_constant_2046:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a3, 2047
+; RV64I-NEXT: blt a1, a3, .LBB17_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB17_2:
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: cmov_sle_i64_constant_2046:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: slti a1, a1, 2047
+; RV64ZBT-NEXT: cmov a0, a1, a0, a2
+; RV64ZBT-NEXT: ret
+ %tobool = icmp sle i64 %b, 2046
+ %cond = select i1 %tobool, i64 %a, i64 %c
+ ret i64 %cond
+}
+
+define i64 @cmov_sle_i64_constant_neg_2049(i64 %a, i64 %b, i64 %c) nounwind {
+; RV64I-LABEL: cmov_sle_i64_constant_neg_2049:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a3, -2048
+; RV64I-NEXT: blt a1, a3, .LBB18_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB18_2:
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: cmov_sle_i64_constant_neg_2049:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: slti a1, a1, -2048
+; RV64ZBT-NEXT: cmov a0, a1, a0, a2
+; RV64ZBT-NEXT: ret
+ %tobool = icmp sle i64 %b, -2049
+ %cond = select i1 %tobool, i64 %a, i64 %c
+ ret i64 %cond
+}
+
+define i64 @cmov_sgt_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
+; RV64I-LABEL: cmov_sgt_i64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: blt a2, a1, .LBB19_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a3
+; RV64I-NEXT: .LBB19_2:
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: cmov_sgt_i64:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: slt a1, a2, a1
+; RV64ZBT-NEXT: cmov a0, a1, a0, a3
+; RV64ZBT-NEXT: ret
+ %tobool = icmp sgt i64 %b, %c
+ %cond = select i1 %tobool, i64 %a, i64 %d
+ ret i64 %cond
+}
+
+define i64 @cmov_sgt_i64_constant_2046(i64 %a, i64 %b, i64 %c) nounwind {
+; RV64I-LABEL: cmov_sgt_i64_constant_2046:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a3, 2046
+; RV64I-NEXT: blt a3, a1, .LBB20_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB20_2:
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: cmov_sgt_i64_constant_2046:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: slti a1, a1, 2047
+; RV64ZBT-NEXT: xori a1, a1, 1
+; RV64ZBT-NEXT: cmov a0, a1, a0, a2
+; RV64ZBT-NEXT: ret
+ %tobool = icmp sgt i64 %b, 2046
+ %cond = select i1 %tobool, i64 %a, i64 %c
+ ret i64 %cond
+}
+
+define i64 @cmov_sgt_i64_constant_neg_2049(i64 %a, i64 %b, i64 %c) nounwind {
+; RV64I-LABEL: cmov_sgt_i64_constant_neg_2049:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a3, 1048575
+; RV64I-NEXT: addiw a3, a3, 2047
+; RV64I-NEXT: blt a3, a1, .LBB21_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB21_2:
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: cmov_sgt_i64_constant_neg_2049:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: slti a1, a1, -2048
+; RV64ZBT-NEXT: xori a1, a1, 1
+; RV64ZBT-NEXT: cmov a0, a1, a0, a2
+; RV64ZBT-NEXT: ret
+ %tobool = icmp sgt i64 %b, -2049
+ %cond = select i1 %tobool, i64 %a, i64 %c
+ ret i64 %cond
+}
+
define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_sge_i64:
; RV64I: # %bb.0:
-; RV64I-NEXT: bge a1, a2, .LBB11_2
+; RV64I-NEXT: bge a1, a2, .LBB22_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: .LBB11_2:
+; RV64I-NEXT: .LBB22_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_sge_i64:
@@ -232,13 +453,56 @@ define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
ret i64 %cond
}
+define i64 @cmov_sge_i64_constant_2047(i64 %a, i64 %b, i64 %c) nounwind {
+; RV64I-LABEL: cmov_sge_i64_constant_2047:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a3, 2046
+; RV64I-NEXT: blt a3, a1, .LBB23_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB23_2:
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: cmov_sge_i64_constant_2047:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: slti a1, a1, 2047
+; RV64ZBT-NEXT: xori a1, a1, 1
+; RV64ZBT-NEXT: cmov a0, a1, a0, a2
+; RV64ZBT-NEXT: ret
+ %tobool = icmp sge i64 %b, 2047
+ %cond = select i1 %tobool, i64 %a, i64 %c
+ ret i64 %cond
+}
+
+define i64 @cmov_sge_i64_constant_neg_2048(i64 %a, i64 %b, i64 %c) nounwind {
+; RV64I-LABEL: cmov_sge_i64_constant_neg_2048:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a3, 1048575
+; RV64I-NEXT: addiw a3, a3, 2047
+; RV64I-NEXT: blt a3, a1, .LBB24_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB24_2:
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: cmov_sge_i64_constant_neg_2048:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: slti a1, a1, -2048
+; RV64ZBT-NEXT: xori a1, a1, 1
+; RV64ZBT-NEXT: cmov a0, a1, a0, a2
+; RV64ZBT-NEXT: ret
+ %tobool = icmp sge i64 %b, -2048
+ %cond = select i1 %tobool, i64 %a, i64 %c
+ ret i64 %cond
+}
+
define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_ule_i64:
; RV64I: # %bb.0:
-; RV64I-NEXT: bgeu a2, a1, .LBB12_2
+; RV64I-NEXT: bgeu a2, a1, .LBB25_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: .LBB12_2:
+; RV64I-NEXT: .LBB25_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_ule_i64:
@@ -251,13 +515,115 @@ define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
ret i64 %cond
}
+define i64 @cmov_ule_i64_constant_2047(i64 %a, i64 %b, i64 %c) nounwind {
+; RV64I-LABEL: cmov_ule_i64_constant_2047:
+; RV64I: # %bb.0:
+; RV64I-NEXT: srli a1, a1, 11
+; RV64I-NEXT: beqz a1, .LBB26_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB26_2:
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: cmov_ule_i64_constant_2047:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: srli a1, a1, 11
+; RV64ZBT-NEXT: cmov a0, a1, a2, a0
+; RV64ZBT-NEXT: ret
+ %tobool = icmp ule i64 %b, 2047
+ %cond = select i1 %tobool, i64 %a, i64 %c
+ ret i64 %cond
+}
+
+define i64 @cmov_ule_i64_constant_neg_2049(i64 %a, i64 %b, i64 %c) nounwind {
+; RV64I-LABEL: cmov_ule_i64_constant_neg_2049:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a3, -2048
+; RV64I-NEXT: bltu a1, a3, .LBB27_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB27_2:
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: cmov_ule_i64_constant_neg_2049:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: sltiu a1, a1, -2048
+; RV64ZBT-NEXT: cmov a0, a1, a0, a2
+; RV64ZBT-NEXT: ret
+ %tobool = icmp ule i64 %b, 18446744073709549567
+ %cond = select i1 %tobool, i64 %a, i64 %c
+ ret i64 %cond
+}
+
+define i64 @cmov_ugt_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
+; RV64I-LABEL: cmov_ugt_i64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: bltu a2, a1, .LBB28_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a3
+; RV64I-NEXT: .LBB28_2:
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: cmov_ugt_i64:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: sltu a1, a2, a1
+; RV64ZBT-NEXT: cmov a0, a1, a0, a3
+; RV64ZBT-NEXT: ret
+ %tobool = icmp ugt i64 %b, %c
+ %cond = select i1 %tobool, i64 %a, i64 %d
+ ret i64 %cond
+}
+
+define i64 @cmov_ugt_i64_constant_2046(i64 %a, i64 %b, i64 %c) nounwind {
+; RV64I-LABEL: cmov_ugt_i64_constant_2046:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a3, 2046
+; RV64I-NEXT: bltu a3, a1, .LBB29_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB29_2:
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: cmov_ugt_i64_constant_2046:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: sltiu a1, a1, 2047
+; RV64ZBT-NEXT: xori a1, a1, 1
+; RV64ZBT-NEXT: cmov a0, a1, a0, a2
+; RV64ZBT-NEXT: ret
+ %tobool = icmp ugt i64 %b, 2046
+ %cond = select i1 %tobool, i64 %a, i64 %c
+ ret i64 %cond
+}
+
+define i64 @cmov_ugt_i64_constant_neg_2049(i64 %a, i64 %b, i64 %c) nounwind {
+; RV64I-LABEL: cmov_ugt_i64_constant_neg_2049:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a3, 1048575
+; RV64I-NEXT: addiw a3, a3, 2047
+; RV64I-NEXT: bltu a3, a1, .LBB30_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB30_2:
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: cmov_ugt_i64_constant_neg_2049:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: sltiu a1, a1, -2048
+; RV64ZBT-NEXT: xori a1, a1, 1
+; RV64ZBT-NEXT: cmov a0, a1, a0, a2
+; RV64ZBT-NEXT: ret
+ %tobool = icmp ugt i64 %b, 18446744073709549567
+ %cond = select i1 %tobool, i64 %a, i64 %c
+ ret i64 %cond
+}
+
define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_uge_i64:
; RV64I: # %bb.0:
-; RV64I-NEXT: bgeu a1, a2, .LBB13_2
+; RV64I-NEXT: bgeu a1, a2, .LBB31_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a3
-; RV64I-NEXT: .LBB13_2:
+; RV64I-NEXT: .LBB31_2:
; RV64I-NEXT: ret
;
; RV64ZBT-LABEL: cmov_uge_i64:
@@ -270,6 +636,49 @@ define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
ret i64 %cond
}
+define i64 @cmov_uge_i64_constant_2047(i64 %a, i64 %b, i64 %c) nounwind {
+; RV64I-LABEL: cmov_uge_i64_constant_2047:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a3, 2046
+; RV64I-NEXT: bltu a3, a1, .LBB32_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB32_2:
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: cmov_uge_i64_constant_2047:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: sltiu a1, a1, 2047
+; RV64ZBT-NEXT: xori a1, a1, 1
+; RV64ZBT-NEXT: cmov a0, a1, a0, a2
+; RV64ZBT-NEXT: ret
+ %tobool = icmp uge i64 %b, 2047
+ %cond = select i1 %tobool, i64 %a, i64 %c
+ ret i64 %cond
+}
+
+define i64 @cmov_uge_i64_constant_neg_2048(i64 %a, i64 %b, i64 %c) nounwind {
+; RV64I-LABEL: cmov_uge_i64_constant_neg_2048:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a3, 1048575
+; RV64I-NEXT: addiw a3, a3, 2047
+; RV64I-NEXT: bltu a3, a1, .LBB33_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB33_2:
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: cmov_uge_i64_constant_neg_2048:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: sltiu a1, a1, -2048
+; RV64ZBT-NEXT: xori a1, a1, 1
+; RV64ZBT-NEXT: cmov a0, a1, a0, a2
+; RV64ZBT-NEXT: ret
+ %tobool = icmp uge i64 %b, 18446744073709549568
+ %cond = select i1 %tobool, i64 %a, i64 %c
+ ret i64 %cond
+}
+
declare i32 @llvm.fshl.i32(i32, i32, i32)
define signext i32 @fshl_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
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