[PATCH] D123163: [TLI] `TargetLowering::SimplifyDemandedVectorElts()`: narrowing bitcast: fill known zero elts from known src bits

[Roman Lebedev via Phabricator via llvm-commits]

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E.g. in

  %i0 = zext <2 x i8> to <2 x i16>
  %i1 = bitcast <2 x i16> to <4 x i8>

the `%i0`'s zero bits are known to be `0xFF00` (upper half of every element is known zero),
but no elements are known to be zero, and for `%i1`, we don't know anything about zero bits,
but the elements under 0xA mask are known to be zero (i.e. the odd elements).

But, we didn't perform such a propagation.

I //think// i wrote that right?


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D123163

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/X86/madd.ll
  llvm/test/CodeGen/X86/shrink_vmul.ll
  llvm/test/CodeGen/X86/slow-pmulld.ll

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