[PATCH] D123111: [AArch64] Make PMMIR_EL1 read-only.

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham created this revision.
simon_tatham added reviewers: labrinea, ostannard, vhscampos.
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The Arm architecture reference manual (ARM DDI 0487H.a section
D13 <https://reviews.llvm.org/D13>.5.12) lists every field in the register as RO, and does not list
an MSR instruction that writes it. So we should be defining it as an
ROSysReg, not an RWSysReg.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D123111

Files:
  llvm/lib/Target/AArch64/AArch64SystemOperands.td
  llvm/test/MC/AArch64/basic-a64-diagnostics.s
  llvm/test/MC/AArch64/basic-a64-instructions.s
  llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt


Index: llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
===================================================================
--- llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
+++ llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
@@ -3308,7 +3308,6 @@
 # CHECK: msr      {{pmintenset_el1|PMINTENSET_EL1}}, x12
 # CHECK: msr      {{pmintenclr_el1|PMINTENCLR_EL1}}, x12
 # CHECK: msr      {{pmovsset_el0|PMOVSSET_EL0}}, x12
-# CHECK: msr      {{pmmir_el1|PMMIR_EL1}}, x12
 # CHECK: msr      {{mair_el1|MAIR_EL1}}, x12
 # CHECK: msr      {{mair_el2|MAIR_EL2}}, x12
 # CHECK: msr      {{mair_el3|MAIR_EL3}}, x12
@@ -3604,7 +3603,6 @@
 # CHECK: mrs      x9, {{pmintenset_el1|PMINTENSET_EL1}}
 # CHECK: mrs      x9, {{pmintenclr_el1|PMINTENCLR_EL1}}
 # CHECK: mrs      x9, {{pmovsset_el0|PMOVSSET_EL0}}
-# CHECK: mrs      x9, {{pmmir_el1|PMMIR_EL1}}
 # CHECK: mrs      x9, {{mair_el1|MAIR_EL1}}
 # CHECK: mrs      x9, {{mair_el2|MAIR_EL2}}
 # CHECK: mrs      x9, {{mair_el3|MAIR_EL3}}
Index: llvm/test/MC/AArch64/basic-a64-instructions.s
===================================================================
--- llvm/test/MC/AArch64/basic-a64-instructions.s
+++ llvm/test/MC/AArch64/basic-a64-instructions.s
@@ -3834,7 +3834,6 @@
 	msr PMINTENSET_EL1, x12
 	msr PMINTENCLR_EL1, x12
 	msr PMOVSSET_EL0, x12
-	msr PMMIR_EL1, x12
 	msr MAIR_EL1, x12
 	msr MAIR_EL2, x12
 	msr MAIR_EL3, x12
@@ -4086,7 +4085,6 @@
 // CHECK: msr      {{pmintenset_el1|PMINTENSET_EL1}}, x12        // encoding: [0x2c,0x9e,0x18,0xd5]
 // CHECK: msr      {{pmintenclr_el1|PMINTENCLR_EL1}}, x12        // encoding: [0x4c,0x9e,0x18,0xd5]
 // CHECK: msr      {{pmovsset_el0|PMOVSSET_EL0}}, x12          // encoding: [0x6c,0x9e,0x1b,0xd5]
-// CHECK: msr      {{pmmir_el1|PMMIR_EL1}}, x12        // encoding: [0xcc,0x9e,0x18,0xd5]
 // CHECK: msr      {{mair_el1|MAIR_EL1}}, x12              // encoding: [0x0c,0xa2,0x18,0xd5]
 // CHECK: msr      {{mair_el2|MAIR_EL2}}, x12              // encoding: [0x0c,0xa2,0x1c,0xd5]
 // CHECK: msr      {{mair_el3|MAIR_EL3}}, x12              // encoding: [0x0c,0xa2,0x1e,0xd5]
Index: llvm/test/MC/AArch64/basic-a64-diagnostics.s
===================================================================
--- llvm/test/MC/AArch64/basic-a64-diagnostics.s
+++ llvm/test/MC/AArch64/basic-a64-diagnostics.s
@@ -3605,6 +3605,7 @@
         msr ID_AA64MMFR1_EL1, x12
         msr PMCEID0_EL0, x12
         msr PMCEID1_EL0, x12
+        msr PMMIR_EL1, x12
         msr RVBAR_EL1, x12
         msr RVBAR_EL2, x12
         msr RVBAR_EL3, x12
@@ -3749,6 +3750,9 @@
 // CHECK-ERROR-NEXT:         msr PMCEID1_EL0, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
+// CHECK-ERROR-NEXT:         msr PMMIR_EL1, x12
+// CHECK-ERROR-NEXT:             ^
+// CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr RVBAR_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
Index: llvm/lib/Target/AArch64/AArch64SystemOperands.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -977,7 +977,7 @@
 def : RWSysReg<"PMINTENSET_EL1",     0b11, 0b000, 0b1001, 0b1110, 0b001>;
 def : RWSysReg<"PMINTENCLR_EL1",     0b11, 0b000, 0b1001, 0b1110, 0b010>;
 def : RWSysReg<"PMOVSSET_EL0",       0b11, 0b011, 0b1001, 0b1110, 0b011>;
-def : RWSysReg<"PMMIR_EL1",          0b11, 0b000, 0b1001, 0b1110, 0b110>;
+def : ROSysReg<"PMMIR_EL1",          0b11, 0b000, 0b1001, 0b1110, 0b110>;
 def : RWSysReg<"MAIR_EL1",           0b11, 0b000, 0b1010, 0b0010, 0b000>;
 def : RWSysReg<"MAIR_EL2",           0b11, 0b100, 0b1010, 0b0010, 0b000>;
 def : RWSysReg<"MAIR_EL3",           0b11, 0b110, 0b1010, 0b0010, 0b000>;


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