[PATCH] D120026: [ARM] Fix ARM backend to correctly use atomic expansion routines.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

In D120026#3427564 <https://reviews.llvm.org/D120026#3427564>, @alanphipps wrote:

> In D120026#3424687 <https://reviews.llvm.org/D120026#3424687>, @efriedma wrote:
>
>> By "the builtins", do you mean you're using compiler-rt with `-DCOMPILER_RT_EXCLUDE_ATOMIC_BUILTIN=Off`?  That implementation probably don't work on a Cortex-M0, unless you've hacked it somehow; it assumes width-1 lock-free atomics are available.
>
> Yes, that's exactly what we're doing.  What should we be doing instead for Cortex-M0?  I don't know a lot about the history of this implementation, but if it doesn't work for M0, why is your change considered acceptable for M0?

There is no way to implement an "atomic" operation on an M0 besides turning off interrupts, and we don't want the builtins library to mess with the interrupt mask.  I'd expect the OS/user to provide the functionality, if they need it.  compiler-rt doesn't provide __sync_* for cortex-m0, for the same reason.

I'm not sure how your setup was working before.  I guess maybe if you only need atomics for C++ static local vars, and you built libc++abi with LIBCXXABI_HAS_NO_THREADS?  If you don't actually need threading/atomics, you can use `-fno-threadsafe-statics` and/or `-mthread-model single`.


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