[llvm] 3c88ff4 - [AArch64] Remove unsued WideningBaseCost. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 3 14:16:44 PDT 2022
Author: David Green
Date: 2022-04-03T22:16:39+01:00
New Revision: 3c88ff44c5a51813b54db289b6faf94e62139009
URL: https://github.com/llvm/llvm-project/commit/3c88ff44c5a51813b54db289b6faf94e62139009
DIFF: https://github.com/llvm/llvm-project/commit/3c88ff44c5a51813b54db289b6faf94e62139009.diff
LOG: [AArch64] Remove unsued WideningBaseCost. NFC
The WideningBaseCost is always 0. This removes it to clean up the code.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index a2ae62b4ec4cf..ceb92582dbdb3 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -105,7 +105,6 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
unsigned PrefLoopLogAlignment = 0;
unsigned MaxBytesForLoopAlignment = 0;
unsigned MaxJumpTableSize = 0;
- unsigned WideningBaseCost = 0;
// ReserveXRegister[i] - X#i is not available as a general purpose register.
BitVector ReserveXRegister;
@@ -235,8 +234,6 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
- unsigned getWideningBaseCost() const { return WideningBaseCost; }
-
/// CPU has TBI (top byte of addresses is ignored during HW address
/// translation) and OS enables it.
bool supportsAddressTopByteIgnored() const;
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index b9f6f49dd04db..0aa39c99dbcd6 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -1765,24 +1765,12 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
// Legalize the type.
std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
-
- // If the instruction is a widening instruction (e.g., uaddl, saddw, etc.),
- // add in the widening overhead specified by the sub-target. Since the
- // extends feeding widening instructions are performed automatically, they
- // aren't present in the generated code and have a zero cost. By adding a
- // widening overhead here, we attach the total cost of the combined operation
- // to the widening instruction.
- InstructionCost Cost = 0;
- if (isWideningInstruction(Ty, Opcode, Args))
- Cost += ST->getWideningBaseCost();
-
int ISD = TLI->InstructionOpcodeToISD(Opcode);
switch (ISD) {
default:
- return Cost + BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info,
- Opd2Info,
- Opd1PropInfo, Opd2PropInfo);
+ return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info,
+ Opd2Info, Opd1PropInfo, Opd2PropInfo);
case ISD::SDIV:
if (Opd2Info == TargetTransformInfo::OK_UniformConstantValue &&
Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) {
@@ -1790,26 +1778,22 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
// normally expanded to the sequence ADD + CMP + SELECT + SRA.
// The OperandValue properties many not be same as that of previous
// operation; conservatively assume OP_None.
- Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind,
- Opd1Info, Opd2Info,
- TargetTransformInfo::OP_None,
- TargetTransformInfo::OP_None);
- Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind,
- Opd1Info, Opd2Info,
- TargetTransformInfo::OP_None,
- TargetTransformInfo::OP_None);
- Cost += getArithmeticInstrCost(Instruction::Select, Ty, CostKind,
- Opd1Info, Opd2Info,
- TargetTransformInfo::OP_None,
+ InstructionCost Cost = getArithmeticInstrCost(
+ Instruction::Add, Ty, CostKind, Opd1Info, Opd2Info,
+ TargetTransformInfo::OP_None, TargetTransformInfo::OP_None);
+ Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Opd1Info,
+ Opd2Info, TargetTransformInfo::OP_None,
TargetTransformInfo::OP_None);
- Cost += getArithmeticInstrCost(Instruction::AShr, Ty, CostKind,
- Opd1Info, Opd2Info,
- TargetTransformInfo::OP_None,
+ Cost += getArithmeticInstrCost(
+ Instruction::Select, Ty, CostKind, Opd1Info, Opd2Info,
+ TargetTransformInfo::OP_None, TargetTransformInfo::OP_None);
+ Cost += getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Opd1Info,
+ Opd2Info, TargetTransformInfo::OP_None,
TargetTransformInfo::OP_None);
return Cost;
}
LLVM_FALLTHROUGH;
- case ISD::UDIV:
+ case ISD::UDIV: {
if (Opd2Info == TargetTransformInfo::OK_UniformConstantValue) {
auto VT = TLI->getValueType(DL, Ty);
if (TLI->isOperationLegalOrCustom(ISD::MULHU, VT)) {
@@ -1829,9 +1813,8 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
}
}
- Cost += BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info,
- Opd2Info,
- Opd1PropInfo, Opd2PropInfo);
+ InstructionCost Cost = BaseT::getArithmeticInstrCost(
+ Opcode, Ty, CostKind, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo);
if (Ty->isVectorTy()) {
// On AArch64, vector divisions are not supported natively and are
// expanded into scalar divisions of each pair of elements.
@@ -1846,10 +1829,10 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
Cost += Cost;
}
return Cost;
-
+ }
case ISD::MUL:
if (LT.second != MVT::v2i64)
- return (Cost + 1) * LT.first;
+ return LT.first;
// Since we do not have a MUL.2d instruction, a mul <2 x i64> is expensive
// as elements are extracted from the vectors and the muls scalarized.
// As getScalarizationOverhead is a bit too pessimistic, we estimate the
@@ -1869,7 +1852,7 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
case ISD::SHL:
// These nodes are marked as 'custom' for combining purposes only.
// We know that they are legal. See LowerAdd in ISelLowering.
- return (Cost + 1) * LT.first;
+ return LT.first;
case ISD::FADD:
case ISD::FSUB:
@@ -1879,11 +1862,10 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
// These nodes are marked as 'custom' just to lower them to SVE.
// We know said lowering will incur no additional cost.
if (!Ty->getScalarType()->isFP128Ty())
- return (Cost + 2) * LT.first;
+ return 2 * LT.first;
- return Cost + BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info,
- Opd2Info,
- Opd1PropInfo, Opd2PropInfo);
+ return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info,
+ Opd2Info, Opd1PropInfo, Opd2PropInfo);
}
}
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