[PATCH] D122829: [AArch64] Optimize SDIV with pow2 constant divisor

[chenglin.bi via Phabricator via llvm-commits]

bcl5980 added a comment.

And one other point is:
Case @dont_fold_srem_i16_smax save 6 instructions with 3 extra add+shift
Case @dont_fold_srem_power_of_two, it save a 9 instructions with 1 extra add+shift
So maybe we can use the general path for vector case at least?


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https://reviews.llvm.org/D122829