[PATCH] D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: llvm/lib/IR/AutoUpgrade.cpp:4601
 
+  if (T.isRISCV() && T.isArch64Bit()) {
+    auto I = DL.find("-n64-");
----------------
Comment?


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll:1077
+; CHECK-ASM-NEXT:    add a3, a4, a3
+; CHECK-ASM-NEXT:    add a1, a1, a3
 ; CHECK-ASM-NEXT:  .LBB12_6: # =>This Inner Loop Header: Depth=1
----------------
This is a regression


================
Comment at: llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp:35
+  
+  EXPECT_EQ(UpgradeDataLayoutString("e-m:e-p:64:64-i64:64-i128:128-n64-S128",
+                                    "riscv64"),
----------------
Comment like AMDGPU?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116735/new/

https://reviews.llvm.org/D116735