[PATCH] D122860: [RISCV][RVV] Add FPRndModeOp to PseudoVFCVT instructions

[ShihPo Hung via Phabricator via llvm-commits]

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Rounding mode rtz  & rod are supported by vfcvt statically,
while other rounding modes such as rdn & rup are supported dynamically and controlled by FRM register, which also affects scalar floating-point operations.

This patch adds an additional operand to carry round-mode information in vfcvt pseudos.
Lowering and instruction selection can specify the needed round mode imm. value and let the backend deal with the round mode change at MachineInstr level at later stage.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D122860

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/lib/Target/RISCV/RISCVMCInstLower.cpp

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