[llvm] 62dd367 - [RISCV] Supplement SDNode patterns for vfwmul/vfwadd/vfwsub
Lian Wang via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 31 20:10:12 PDT 2022
Author: Lian Wang
Date: 2022-04-01T03:09:50Z
New Revision: 62dd3674bcf88f60077460f80b6444fb7ac0adf4
URL: https://github.com/llvm/llvm-project/commit/62dd3674bcf88f60077460f80b6444fb7ac0adf4
DIFF: https://github.com/llvm/llvm-project/commit/62dd3674bcf88f60077460f80b6444fb7ac0adf4.diff
LOG: [RISCV] Supplement SDNode patterns for vfwmul/vfwadd/vfwsub
Reviewed By: jacquesguan
Differential Revision: https://reviews.llvm.org/D122720
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index c1c8fc56ca9a2..37b772c465afd 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -415,6 +415,11 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF<SDNode op, string instruction_name> {
(!cast<Instruction>(instruction_name#"_V"#vti.Vti.ScalarSuffix#"_"#vti.Vti.LMul.MX)
vti.Vti.RegClass:$rs2, vti.Vti.ScalarRegClass:$rs1,
vti.Vti.AVL, vti.Vti.Log2SEW)>;
+ def : Pat<(op (vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector vti.Vti.RegClass:$rs2))),
+ (vti.Wti.Vector (SplatFPOp (fpext_oneuse vti.Vti.ScalarRegClass:$rs1)))),
+ (!cast<Instruction>(instruction_name#"_V"#vti.Vti.ScalarSuffix#"_"#vti.Vti.LMul.MX)
+ vti.Vti.RegClass:$rs2, vti.Vti.ScalarRegClass:$rs1,
+ vti.Vti.AVL, vti.Vti.Log2SEW)>;
}
}
@@ -430,6 +435,11 @@ multiclass VPatWidenBinaryFPSDNode_WV_WF<SDNode op, string instruction_name> {
(!cast<Instruction>(instruction_name#"_W"#vti.Vti.ScalarSuffix#"_"#vti.Vti.LMul.MX)
vti.Wti.RegClass:$rs2, vti.Vti.ScalarRegClass:$rs1,
vti.Vti.AVL, vti.Vti.Log2SEW)>;
+ def : Pat<(op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
+ (vti.Wti.Vector (SplatFPOp (fpext_oneuse vti.Vti.ScalarRegClass:$rs1)))),
+ (!cast<Instruction>(instruction_name#"_W"#vti.Vti.ScalarSuffix#"_"#vti.Vti.LMul.MX)
+ vti.Wti.RegClass:$rs2, vti.Vti.ScalarRegClass:$rs1,
+ vti.Vti.AVL, vti.Vti.Log2SEW)>;
}
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
index 0fab7e66cba10..b71c475318316 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
@@ -32,6 +32,21 @@ define <vscale x 1 x double> @vfwadd_vf_nxv1f64(<vscale x 1 x float> %va, float
ret <vscale x 1 x double> %ve
}
+define <vscale x 1 x double> @vfwadd_vf_nxv1f64_2(<vscale x 1 x float> %va, float %b) {
+; CHECK-LABEL: vfwadd_vf_nxv1f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vfwadd.vf v9, v8, fa0
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %fpext = fpext float %b to double
+ %head = insertelement <vscale x 1 x double> poison, double %fpext, i32 0
+ %splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
+ %vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
+ %ve = fadd <vscale x 1 x double> %vc, %splat
+ ret <vscale x 1 x double> %ve
+}
+
define <vscale x 1 x double> @vfwadd_wv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x float> %vb) {
; CHECK-LABEL: vfwadd_wv_nxv1f64:
; CHECK: # %bb.0:
@@ -57,6 +72,19 @@ define <vscale x 1 x double> @vfwadd_wf_nxv1f64(<vscale x 1 x double> %va, float
ret <vscale x 1 x double> %vd
}
+define <vscale x 1 x double> @vfwadd_wf_nxv1f64_2(<vscale x 1 x double> %va, float %b) {
+; CHECK-LABEL: vfwadd_wf_nxv1f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vfwadd.wf v8, v8, fa0
+; CHECK-NEXT: ret
+ %fpext = fpext float %b to double
+ %head = insertelement <vscale x 1 x double> poison, double %fpext, i32 0
+ %splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
+ %vd = fadd <vscale x 1 x double> %va, %splat
+ ret <vscale x 1 x double> %vd
+}
+
define <vscale x 2 x double> @vfwadd_vv_nxv2f64(<vscale x 2 x float> %va, <vscale x 2 x float> %vb) {
; CHECK-LABEL: vfwadd_vv_nxv2f64:
; CHECK: # %bb.0:
@@ -85,6 +113,21 @@ define <vscale x 2 x double> @vfwadd_vf_nxv2f64(<vscale x 2 x float> %va, float
ret <vscale x 2 x double> %ve
}
+define <vscale x 2 x double> @vfwadd_vf_nxv2f64_2(<vscale x 2 x float> %va, float %b) {
+; CHECK-LABEL: vfwadd_vf_nxv2f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT: vfwadd.vf v10, v8, fa0
+; CHECK-NEXT: vmv2r.v v8, v10
+; CHECK-NEXT: ret
+ %fpext = fpext float %b to double
+ %head = insertelement <vscale x 2 x double> poison, double %fpext, i32 0
+ %splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
+ %vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
+ %ve = fadd <vscale x 2 x double> %vc, %splat
+ ret <vscale x 2 x double> %ve
+}
+
define <vscale x 2 x double> @vfwadd_wv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x float> %vb) {
; CHECK-LABEL: vfwadd_wv_nxv2f64:
; CHECK: # %bb.0:
@@ -110,6 +153,19 @@ define <vscale x 2 x double> @vfwadd_wf_nxv2f64(<vscale x 2 x double> %va, float
ret <vscale x 2 x double> %vd
}
+define <vscale x 2 x double> @vfwadd_wf_nxv2f64_2(<vscale x 2 x double> %va, float %b) {
+; CHECK-LABEL: vfwadd_wf_nxv2f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT: vfwadd.wf v8, v8, fa0
+; CHECK-NEXT: ret
+ %fpext = fpext float %b to double
+ %head = insertelement <vscale x 2 x double> poison, double %fpext, i32 0
+ %splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
+ %vd = fadd <vscale x 2 x double> %va, %splat
+ ret <vscale x 2 x double> %vd
+}
+
define <vscale x 4 x double> @vfwadd_vv_nxv4f64(<vscale x 4 x float> %va, <vscale x 4 x float> %vb) {
; CHECK-LABEL: vfwadd_vv_nxv4f64:
; CHECK: # %bb.0:
@@ -138,6 +194,21 @@ define <vscale x 4 x double> @vfwadd_vf_nxv4f64(<vscale x 4 x float> %va, float
ret <vscale x 4 x double> %ve
}
+define <vscale x 4 x double> @vfwadd_vf_nxv4f64_2(<vscale x 4 x float> %va, float %b) {
+; CHECK-LABEL: vfwadd_vf_nxv4f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vfwadd.vf v12, v8, fa0
+; CHECK-NEXT: vmv4r.v v8, v12
+; CHECK-NEXT: ret
+ %fpext = fpext float %b to double
+ %head = insertelement <vscale x 4 x double> poison, double %fpext, i32 0
+ %splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> poison, <vscale x 4 x i32> zeroinitializer
+ %vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
+ %ve = fadd <vscale x 4 x double> %vc, %splat
+ ret <vscale x 4 x double> %ve
+}
+
define <vscale x 4 x double> @vfwadd_wv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x float> %vb) {
; CHECK-LABEL: vfwadd_wv_nxv4f64:
; CHECK: # %bb.0:
@@ -163,6 +234,19 @@ define <vscale x 4 x double> @vfwadd_wf_nxv4f64(<vscale x 4 x double> %va, float
ret <vscale x 4 x double> %vd
}
+define <vscale x 4 x double> @vfwadd_wf_nxv4f64_2(<vscale x 4 x double> %va, float %b) {
+; CHECK-LABEL: vfwadd_wf_nxv4f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vfwadd.wf v8, v8, fa0
+; CHECK-NEXT: ret
+ %fpext = fpext float %b to double
+ %head = insertelement <vscale x 4 x double> poison, double %fpext, i32 0
+ %splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> poison, <vscale x 4 x i32> zeroinitializer
+ %vd = fadd <vscale x 4 x double> %va, %splat
+ ret <vscale x 4 x double> %vd
+}
+
define <vscale x 8 x double> @vfwadd_vv_nxv8f64(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: vfwadd_vv_nxv8f64:
; CHECK: # %bb.0:
@@ -191,6 +275,21 @@ define <vscale x 8 x double> @vfwadd_vf_nxv8f64(<vscale x 8 x float> %va, float
ret <vscale x 8 x double> %ve
}
+define <vscale x 8 x double> @vfwadd_vf_nxv8f64_2(<vscale x 8 x float> %va, float %b) {
+; CHECK-LABEL: vfwadd_vf_nxv8f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vfwadd.vf v16, v8, fa0
+; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: ret
+ %fpext = fpext float %b to double
+ %head = insertelement <vscale x 8 x double> poison, double %fpext, i32 0
+ %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
+ %vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
+ %ve = fadd <vscale x 8 x double> %vc, %splat
+ ret <vscale x 8 x double> %ve
+}
+
define <vscale x 8 x double> @vfwadd_wv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: vfwadd_wv_nxv8f64:
; CHECK: # %bb.0:
@@ -215,3 +314,16 @@ define <vscale x 8 x double> @vfwadd_wf_nxv8f64(<vscale x 8 x double> %va, float
%vd = fadd <vscale x 8 x double> %va, %vc
ret <vscale x 8 x double> %vd
}
+
+define <vscale x 8 x double> @vfwadd_wf_nxv8f64_2(<vscale x 8 x double> %va, float %b) {
+; CHECK-LABEL: vfwadd_wf_nxv8f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vfwadd.wf v8, v8, fa0
+; CHECK-NEXT: ret
+ %fpext = fpext float %b to double
+ %head = insertelement <vscale x 8 x double> poison, double %fpext, i32 0
+ %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
+ %vd = fadd <vscale x 8 x double> %va, %splat
+ ret <vscale x 8 x double> %vd
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll
index 569ef9cce357f..a61d8f11b58b9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll
@@ -32,6 +32,21 @@ define <vscale x 1 x double> @vfwmul_vf_nxv1f64(<vscale x 1 x float> %va, float
ret <vscale x 1 x double> %ve
}
+define <vscale x 1 x double> @vfwmul_vf_nxv1f64_2(<vscale x 1 x float> %va, float %b) {
+; CHECK-LABEL: vfwmul_vf_nxv1f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vfwmul.vf v9, v8, fa0
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %fpext = fpext float %b to double
+ %head = insertelement <vscale x 1 x double> poison, double %fpext, i32 0
+ %splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
+ %vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
+ %ve = fmul <vscale x 1 x double> %vc, %splat
+ ret <vscale x 1 x double> %ve
+}
+
define <vscale x 2 x double> @vfwmul_vv_nxv2f64(<vscale x 2 x float> %va, <vscale x 2 x float> %vb) {
; CHECK-LABEL: vfwmul_vv_nxv2f64:
; CHECK: # %bb.0:
@@ -60,6 +75,21 @@ define <vscale x 2 x double> @vfwmul_vf_nxv2f64(<vscale x 2 x float> %va, float
ret <vscale x 2 x double> %ve
}
+define <vscale x 2 x double> @vfwmul_vf_nxv2f64_2(<vscale x 2 x float> %va, float %b) {
+; CHECK-LABEL: vfwmul_vf_nxv2f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT: vfwmul.vf v10, v8, fa0
+; CHECK-NEXT: vmv2r.v v8, v10
+; CHECK-NEXT: ret
+ %fpext = fpext float %b to double
+ %head = insertelement <vscale x 2 x double> poison, double %fpext, i32 0
+ %splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
+ %vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
+ %ve = fmul <vscale x 2 x double> %vc, %splat
+ ret <vscale x 2 x double> %ve
+}
+
define <vscale x 4 x double> @vfwmul_vv_nxv4f64(<vscale x 4 x float> %va, <vscale x 4 x float> %vb) {
; CHECK-LABEL: vfwmul_vv_nxv4f64:
; CHECK: # %bb.0:
@@ -88,6 +118,21 @@ define <vscale x 4 x double> @vfwmul_vf_nxv4f64(<vscale x 4 x float> %va, float
ret <vscale x 4 x double> %ve
}
+define <vscale x 4 x double> @vfwmul_vf_nxv4f64_2(<vscale x 4 x float> %va, float %b) {
+; CHECK-LABEL: vfwmul_vf_nxv4f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vfwmul.vf v12, v8, fa0
+; CHECK-NEXT: vmv4r.v v8, v12
+; CHECK-NEXT: ret
+ %fpext = fpext float %b to double
+ %head = insertelement <vscale x 4 x double> poison, double %fpext, i32 0
+ %splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> poison, <vscale x 4 x i32> zeroinitializer
+ %vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
+ %ve = fmul <vscale x 4 x double> %vc, %splat
+ ret <vscale x 4 x double> %ve
+}
+
define <vscale x 8 x double> @vfwmul_vv_nxv8f64(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: vfwmul_vv_nxv8f64:
; CHECK: # %bb.0:
@@ -115,3 +160,18 @@ define <vscale x 8 x double> @vfwmul_vf_nxv8f64(<vscale x 8 x float> %va, float
%ve = fmul <vscale x 8 x double> %vc, %vd
ret <vscale x 8 x double> %ve
}
+
+define <vscale x 8 x double> @vfwmul_vf_nxv8f64_2(<vscale x 8 x float> %va, float %b) {
+; CHECK-LABEL: vfwmul_vf_nxv8f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vfwmul.vf v16, v8, fa0
+; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: ret
+ %fpext = fpext float %b to double
+ %head = insertelement <vscale x 8 x double> poison, double %fpext, i32 0
+ %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
+ %vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
+ %ve = fmul <vscale x 8 x double> %vc, %splat
+ ret <vscale x 8 x double> %ve
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
index 43b5f8fd87e36..25b625559aacd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
@@ -32,6 +32,21 @@ define <vscale x 1 x double> @vfwsub_vf_nxv1f64(<vscale x 1 x float> %va, float
ret <vscale x 1 x double> %ve
}
+define <vscale x 1 x double> @vfwsub_vf_nxv1f64_2(<vscale x 1 x float> %va, float %b) {
+; CHECK-LABEL: vfwsub_vf_nxv1f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vfwsub.vf v9, v8, fa0
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %fpext = fpext float %b to double
+ %head = insertelement <vscale x 1 x double> poison, double %fpext, i32 0
+ %splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
+ %vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
+ %ve = fsub <vscale x 1 x double> %vc, %splat
+ ret <vscale x 1 x double> %ve
+}
+
define <vscale x 1 x double> @vfwsub_wv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x float> %vb) {
; CHECK-LABEL: vfwsub_wv_nxv1f64:
; CHECK: # %bb.0:
@@ -57,6 +72,19 @@ define <vscale x 1 x double> @vfwsub_wf_nxv1f64(<vscale x 1 x double> %va, float
ret <vscale x 1 x double> %vd
}
+define <vscale x 1 x double> @vfwsub_wf_nxv1f64_2(<vscale x 1 x double> %va, float %b) {
+; CHECK-LABEL: vfwsub_wf_nxv1f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vfwsub.wf v8, v8, fa0
+; CHECK-NEXT: ret
+ %fpext = fpext float %b to double
+ %head = insertelement <vscale x 1 x double> poison, double %fpext, i32 0
+ %splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
+ %vd = fsub <vscale x 1 x double> %va, %splat
+ ret <vscale x 1 x double> %vd
+}
+
define <vscale x 2 x double> @vfwsub_vv_nxv2f64(<vscale x 2 x float> %va, <vscale x 2 x float> %vb) {
; CHECK-LABEL: vfwsub_vv_nxv2f64:
; CHECK: # %bb.0:
@@ -85,6 +113,21 @@ define <vscale x 2 x double> @vfwsub_vf_nxv2f64(<vscale x 2 x float> %va, float
ret <vscale x 2 x double> %ve
}
+define <vscale x 2 x double> @vfwsub_vf_nxv2f64_2(<vscale x 2 x float> %va, float %b) {
+; CHECK-LABEL: vfwsub_vf_nxv2f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT: vfwsub.vf v10, v8, fa0
+; CHECK-NEXT: vmv2r.v v8, v10
+; CHECK-NEXT: ret
+ %fpext = fpext float %b to double
+ %head = insertelement <vscale x 2 x double> poison, double %fpext, i32 0
+ %splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
+ %vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
+ %ve = fsub <vscale x 2 x double> %vc, %splat
+ ret <vscale x 2 x double> %ve
+}
+
define <vscale x 2 x double> @vfwsub_wv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x float> %vb) {
; CHECK-LABEL: vfwsub_wv_nxv2f64:
; CHECK: # %bb.0:
@@ -110,6 +153,19 @@ define <vscale x 2 x double> @vfwsub_wf_nxv2f64(<vscale x 2 x double> %va, float
ret <vscale x 2 x double> %vd
}
+define <vscale x 2 x double> @vfwsub_wf_nxv2f64_2(<vscale x 2 x double> %va, float %b) {
+; CHECK-LABEL: vfwsub_wf_nxv2f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT: vfwsub.wf v8, v8, fa0
+; CHECK-NEXT: ret
+ %fpext = fpext float %b to double
+ %head = insertelement <vscale x 2 x double> poison, double %fpext, i32 0
+ %splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
+ %vd = fsub <vscale x 2 x double> %va, %splat
+ ret <vscale x 2 x double> %vd
+}
+
define <vscale x 4 x double> @vfwsub_vv_nxv4f64(<vscale x 4 x float> %va, <vscale x 4 x float> %vb) {
; CHECK-LABEL: vfwsub_vv_nxv4f64:
; CHECK: # %bb.0:
@@ -138,6 +194,21 @@ define <vscale x 4 x double> @vfwsub_vf_nxv4f64(<vscale x 4 x float> %va, float
ret <vscale x 4 x double> %ve
}
+define <vscale x 4 x double> @vfwsub_vf_nxv4f64_2(<vscale x 4 x float> %va, float %b) {
+; CHECK-LABEL: vfwsub_vf_nxv4f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vfwsub.vf v12, v8, fa0
+; CHECK-NEXT: vmv4r.v v8, v12
+; CHECK-NEXT: ret
+ %fpext = fpext float %b to double
+ %head = insertelement <vscale x 4 x double> poison, double %fpext, i32 0
+ %splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> poison, <vscale x 4 x i32> zeroinitializer
+ %vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
+ %ve = fsub <vscale x 4 x double> %vc, %splat
+ ret <vscale x 4 x double> %ve
+}
+
define <vscale x 4 x double> @vfwsub_wv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x float> %vb) {
; CHECK-LABEL: vfwsub_wv_nxv4f64:
; CHECK: # %bb.0:
@@ -163,6 +234,19 @@ define <vscale x 4 x double> @vfwsub_wf_nxv4f64(<vscale x 4 x double> %va, float
ret <vscale x 4 x double> %vd
}
+define <vscale x 4 x double> @vfwsub_wf_nxv4f64_2(<vscale x 4 x double> %va, float %b) {
+; CHECK-LABEL: vfwsub_wf_nxv4f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vfwsub.wf v8, v8, fa0
+; CHECK-NEXT: ret
+ %fpext = fpext float %b to double
+ %head = insertelement <vscale x 4 x double> poison, double %fpext, i32 0
+ %splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> poison, <vscale x 4 x i32> zeroinitializer
+ %vd = fsub <vscale x 4 x double> %va, %splat
+ ret <vscale x 4 x double> %vd
+}
+
define <vscale x 8 x double> @vfwsub_vv_nxv8f64(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: vfwsub_vv_nxv8f64:
; CHECK: # %bb.0:
@@ -191,6 +275,21 @@ define <vscale x 8 x double> @vfwsub_vf_nxv8f64(<vscale x 8 x float> %va, float
ret <vscale x 8 x double> %ve
}
+define <vscale x 8 x double> @vfwsub_vf_nxv8f64_2(<vscale x 8 x float> %va, float %b) {
+; CHECK-LABEL: vfwsub_vf_nxv8f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vfwsub.vf v16, v8, fa0
+; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: ret
+ %fpext = fpext float %b to double
+ %head = insertelement <vscale x 8 x double> poison, double %fpext, i32 0
+ %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
+ %vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
+ %ve = fsub <vscale x 8 x double> %vc, %splat
+ ret <vscale x 8 x double> %ve
+}
+
define <vscale x 8 x double> @vfwsub_wv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: vfwsub_wv_nxv8f64:
; CHECK: # %bb.0:
@@ -215,3 +314,16 @@ define <vscale x 8 x double> @vfwsub_wf_nxv8f64(<vscale x 8 x double> %va, float
%vd = fsub <vscale x 8 x double> %va, %vc
ret <vscale x 8 x double> %vd
}
+
+define <vscale x 8 x double> @vfwsub_wf_nxv8f64_2(<vscale x 8 x double> %va, float %b) {
+; CHECK-LABEL: vfwsub_wf_nxv8f64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vfwsub.wf v8, v8, fa0
+; CHECK-NEXT: ret
+ %fpext = fpext float %b to double
+ %head = insertelement <vscale x 8 x double> poison, double %fpext, i32 0
+ %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
+ %vd = fsub <vscale x 8 x double> %va, %splat
+ ret <vscale x 8 x double> %vd
+}
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