[PATCH] D122701: [RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases

[Craig Topper via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG447750053328: [RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D122701?vs=419040&id=419235#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122701/new/

https://reviews.llvm.org/D122701

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/test/CodeGen/RISCV/bitreverse-shift.ll
  llvm/test/CodeGen/RISCV/bswap-shift.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll
  llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
  llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D122701.419235.patch
Type: text/x-patch
Size: 9205 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220330/712a8a20/attachment.bin>