[PATCH] D122701: [RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases

[Luís Marques via Phabricator via llvm-commits]

luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.

LGTM.

> I'm not checking the C extension since we have relatively poor test coverage of the C extension.

Note that in a TODO?

> My only concern would be if the shift+andi had better latency/throughput on a particular CPU.

If someone can list CPUs where that's true please chime in. The only one I'm aware of is (depending on configuration) the PicoRV32, so this seems like a good tradeoff.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122701/new/

https://reviews.llvm.org/D122701