[PATCH] D122702: [RISCV] Add CMIX isel pattern for (xor (and (xor rs1, rs3), rs2), rs3)

[LiqinWeng via Phabricator via llvm-commits]

Miss_Grape added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rv32zbt.ll:92
+  %and = and i64 %xor, %b
+  %xor1 = and i64 %and, %c
+  ret i64 %xor1
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craig.topper wrote:
> This `and` should be `xor`?
fixed


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122702/new/

https://reviews.llvm.org/D122702