[PATCH] D122563: [RISCV] Add DAGCombine to fold base operation and reduction.

[Yeting Kuo via Phabricator via llvm-commits]

fakepaper56 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7254
+  if (Opc == ISD::FADD && !N->getFlags().hasAllowReassociation() &&
+      ReduceIdx == 0)
+    return SDValue();
----------------
craig.topper wrote:
> The ReduceIdx is relevant here. The order of the fadd operands doesn't matter. The reduce operation is before the fadd, we need to know if the fadd can be moved before the reduce.
VECREDUCE_FADD_VL always has reassociation, so I think I only need to check `N->getFlags().hasAllowReassociation()` to make sure fadd can be moved before the reduce.


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  https://reviews.llvm.org/D122563/new/

https://reviews.llvm.org/D122563