[PATCH] D122653: [AMDGPU] Document the intended semantics of llvm.amdgcn.s.buffer.load

[David Stuttard via Phabricator via llvm-commits]

dstuttard added inline comments.


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Comment at: llvm/include/llvm/IR/IntrinsicsAMDGPU.td:957
   [llvm_v4i32_ty,     // rsrc(SGPR)
    llvm_i32_ty,       // byte offset(SGPR/imm)
    llvm_i32_ty],      // cachepolicy(imm; bit 0 = glc, bit 2 = dlc)
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The added description would imply that this should be updated too (since it isn't necessarily SGPR/imm)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122653/new/

https://reviews.llvm.org/D122653