[PATCH] D122566: [AArch64] Set MaxBytesForLoopAlignment for more targets

[Nicholas Guy via Phabricator via llvm-commits]

NickGuy created this revision.
NickGuy added reviewers: dmgreen, samtebbs.
NickGuy added a project: LLVM.
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Further implementation of D114590 <https://reviews.llvm.org/D114590> for the AArch64 backend. Specifying the max padding allowed for loop alignment for further AArch64 targets.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D122566

Files:
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp


Index: llvm/lib/Target/AArch64/AArch64Subtarget.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -79,14 +79,17 @@
     CacheLineSize = 64;
     break;
   case CortexA35:
+    MaxBytesForLoopAlignment = 8;
     break;
   case CortexA53:
   case CortexA55:
     PrefFunctionLogAlignment = 4;
+    MaxBytesForLoopAlignment = 8;
     break;
   case CortexA57:
     MaxInterleaveFactor = 4;
     PrefFunctionLogAlignment = 4;
+    MaxBytesForLoopAlignment = 8;
     break;
   case CortexA65:
     PrefFunctionLogAlignment = 3;
@@ -102,6 +105,7 @@
   case CortexX1:
   case CortexX1C:
     PrefFunctionLogAlignment = 4;
+    MaxBytesForLoopAlignment = 8;
     break;
   case CortexA510:
   case CortexA710:


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