[PATCH] D122540: [X86] Fix handling of maskmovdqu in x32 differently

[Harald van Dijk via Phabricator via llvm-commits]

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This reverts the functional changes of commit a8ad9170543906fc58336ab736a109fb42082fbf <https://reviews.llvm.org/rGa8ad9170543906fc58336ab736a109fb42082fbf> but keeps its tests, and reimplements the functionality by reusing the existing 32-bit MASKMOVDQU and VMASKMOVDQU instructions which were previously predicated on Not64BitMode. This reimplementation restores the disassembly of a class of instructions, which will see a test added in followup patch D122449 <https://reviews.llvm.org/D122449>.

      

These instructions are in 64-bit mode special cased in X86MCInstLower::Lower, because we use flags with one meaning for subtly different things: we have an AdSize32 class which indicates both that the instruction needs a 0x67 prefix and that the text form of the instruction implies a 0x67 prefix. These instructions are special in needing a 0x67 prefix but having a text form that does *not* imply a 0x67 prefix, so we encode this in MCInst as an instruction that has an explicit address size override.

      

Note that originally VMASKMOVDQU64 was special cased to be excluded from disassembly, as we cannot distinguish between VMASKMOVDQU and VMASKMOVDQU64 and rely on the fact that these are indistinguishable, or close enough to it, at the MCInst level that it does not matter which we use. Because VMASKMOVDQU now receives special casing, even though it does not make a difference in the current implementation, as a precaution VMASKMOVDQU is excluded from disassembly rather than VMASKMOVDQU64.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D122540

Files:
  llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/Target/X86/X86MCInstLower.cpp
  llvm/lib/Target/X86/X86ScheduleBtVer2.td
  llvm/utils/TableGen/X86DisassemblerTables.cpp
  llvm/utils/TableGen/X86RecognizableInstr.cpp

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