[llvm] 4a48742 - [X86][tablgen] Extract common functions in X86EVEX2VEXTablesEmitter.cpp and X86FoldTablesEmitter.cpp to avoid duplicated code. NFC
Shengchen Kan via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 26 17:47:42 PDT 2022
Author: Shengchen Kan
Date: 2022-03-27T08:47:18+08:00
New Revision: 4a4874292258391e976d3a7e508278ca58418bc1
URL: https://github.com/llvm/llvm-project/commit/4a4874292258391e976d3a7e508278ca58418bc1
DIFF: https://github.com/llvm/llvm-project/commit/4a4874292258391e976d3a7e508278ca58418bc1.diff
LOG: [X86][tablgen] Extract common functions in X86EVEX2VEXTablesEmitter.cpp and X86FoldTablesEmitter.cpp to avoid duplicated code. NFC
Added:
Modified:
llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
llvm/utils/TableGen/X86FoldTablesEmitter.cpp
llvm/utils/TableGen/X86RecognizableInstr.cpp
llvm/utils/TableGen/X86RecognizableInstr.h
Removed:
################################################################################
diff --git a/llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp b/llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
index 627c5c6882ce2..1384330ee8a12 100644
--- a/llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
@@ -18,6 +18,7 @@
#include "llvm/TableGen/TableGenBackend.h"
using namespace llvm;
+using namespace X86Disassembler;
namespace {
@@ -110,8 +111,8 @@ class IsMatch {
IsMatch(const CodeGenInstruction *EVEXInst) : EVEXInst(EVEXInst) {}
bool operator()(const CodeGenInstruction *VEXInst) {
- X86Disassembler::RecognizableInstrBase VEXRI(*VEXInst);
- X86Disassembler::RecognizableInstrBase EVEXRI(*EVEXInst);
+ RecognizableInstrBase VEXRI(*VEXInst);
+ RecognizableInstrBase EVEXRI(*EVEXInst);
bool VEX_W = VEXRI.HasVEX_W;
bool EVEX_W = EVEXRI.HasVEX_W;
bool VEX_WIG = VEXRI.IgnoresVEX_W;
@@ -159,31 +160,6 @@ class IsMatch {
return true;
}
-
-private:
- static inline bool isRegisterOperand(const Record *Rec) {
- return Rec->isSubClassOf("RegisterClass") ||
- Rec->isSubClassOf("RegisterOperand");
- }
-
- static inline bool isMemoryOperand(const Record *Rec) {
- return Rec->isSubClassOf("Operand") &&
- Rec->getValueAsString("OperandType") == "OPERAND_MEMORY";
- }
-
- static inline bool isImmediateOperand(const Record *Rec) {
- return Rec->isSubClassOf("Operand") &&
- Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE";
- }
-
- static inline unsigned int getRegOperandSize(const Record *RegRec) {
- if (RegRec->isSubClassOf("RegisterClass"))
- return RegRec->getValueAsInt("Alignment");
- if (RegRec->isSubClassOf("RegisterOperand"))
- return RegRec->getValueAsDef("RegClass")->getValueAsInt("Alignment");
-
- llvm_unreachable("Register operand's size not known!");
- }
};
void X86EVEX2VEXTablesEmitter::run(raw_ostream &OS) {
@@ -209,7 +185,7 @@ void X86EVEX2VEXTablesEmitter::run(raw_ostream &OS) {
// Filter non-X86 instructions.
if (!Def->isSubClassOf("X86Inst"))
continue;
- X86Disassembler::RecognizableInstrBase RI(*Inst);
+ RecognizableInstrBase RI(*Inst);
// Add VEX encoded instructions to one of VEXInsts vectors according to
// it's opcode.
diff --git a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
index eb52ebd736f71..5f6e983f608c0 100644
--- a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
@@ -18,6 +18,7 @@
#include "llvm/TableGen/TableGenBackend.h"
using namespace llvm;
+using namespace X86Disassembler;
namespace {
@@ -212,42 +213,6 @@ static inline uint64_t getValueFromBitsInit(const BitsInit *B) {
return Value;
}
-// Return the size of the register operand
-static inline unsigned int getRegOperandSize(const Record *RegRec) {
- if (RegRec->isSubClassOf("RegisterOperand"))
- RegRec = RegRec->getValueAsDef("RegClass");
- if (RegRec->isSubClassOf("RegisterClass"))
- return RegRec->getValueAsListOfDefs("RegTypes")[0]->getValueAsInt("Size");
-
- llvm_unreachable("Register operand's size not known!");
-}
-
-// Return the size of the memory operand
-static inline unsigned getMemOperandSize(const Record *MemRec) {
- if (MemRec->isSubClassOf("Operand")) {
- StringRef Name =
- MemRec->getValueAsDef("ParserMatchClass")->getValueAsString("Name");
- if (Name == "Mem8")
- return 8;
- if (Name == "Mem16")
- return 16;
- if (Name == "Mem32")
- return 32;
- if (Name == "Mem64")
- return 64;
- if (Name == "Mem80")
- return 80;
- if (Name == "Mem128")
- return 128;
- if (Name == "Mem256")
- return 256;
- if (Name == "Mem512")
- return 512;
- }
-
- llvm_unreachable("Memory operand's size not known!");
-}
-
// Return true if the instruction defined as a register flavor.
static inline bool hasRegisterFormat(const Record *Inst) {
const BitsInit *FormBits = Inst->getValueAsBitsInit("FormBits");
@@ -270,21 +235,6 @@ static inline bool isNOREXRegClass(const Record *Op) {
return Op->getName().contains("_NOREX");
}
-static inline bool isRegisterOperand(const Record *Rec) {
- return Rec->isSubClassOf("RegisterClass") ||
- Rec->isSubClassOf("RegisterOperand");
-}
-
-static inline bool isMemoryOperand(const Record *Rec) {
- return Rec->isSubClassOf("Operand") &&
- Rec->getValueAsString("OperandType") == "OPERAND_MEMORY";
-}
-
-static inline bool isImmediateOperand(const Record *Rec) {
- return Rec->isSubClassOf("Operand") &&
- Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE";
-}
-
// Get the alternative instruction pointed by "FoldGenRegForm" field.
static inline const CodeGenInstruction *
getAltRegInst(const CodeGenInstruction *I, const RecordKeeper &Records,
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index 5a6a5f13caf73..f842ce541e886 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -38,6 +38,55 @@ std::string X86Disassembler::getMnemonic(const CodeGenInstruction *I, unsigned V
return Mnemonic.upper();
}
+bool X86Disassembler::isRegisterOperand(const Record *Rec) {
+ return Rec->isSubClassOf("RegisterClass") ||
+ Rec->isSubClassOf("RegisterOperand");
+}
+
+bool X86Disassembler::isMemoryOperand(const Record *Rec) {
+ return Rec->isSubClassOf("Operand") &&
+ Rec->getValueAsString("OperandType") == "OPERAND_MEMORY";
+}
+
+bool X86Disassembler::isImmediateOperand(const Record *Rec) {
+ return Rec->isSubClassOf("Operand") &&
+ Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE";
+}
+
+unsigned X86Disassembler::getRegOperandSize(const Record *RegRec) {
+ if (RegRec->isSubClassOf("RegisterClass"))
+ return RegRec->getValueAsInt("Alignment");
+ if (RegRec->isSubClassOf("RegisterOperand"))
+ return RegRec->getValueAsDef("RegClass")->getValueAsInt("Alignment");
+
+ llvm_unreachable("Register operand's size not known!");
+}
+
+unsigned X86Disassembler::getMemOperandSize(const Record *MemRec) {
+ if (MemRec->isSubClassOf("Operand")) {
+ StringRef Name =
+ MemRec->getValueAsDef("ParserMatchClass")->getValueAsString("Name");
+ if (Name == "Mem8")
+ return 8;
+ if (Name == "Mem16")
+ return 16;
+ if (Name == "Mem32")
+ return 32;
+ if (Name == "Mem64")
+ return 64;
+ if (Name == "Mem80")
+ return 80;
+ if (Name == "Mem128")
+ return 128;
+ if (Name == "Mem256")
+ return 256;
+ if (Name == "Mem512")
+ return 512;
+ }
+
+ llvm_unreachable("Memory operand's size not known!");
+}
+
/// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
/// Useful for switch statements and the like.
///
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.h b/llvm/utils/TableGen/X86RecognizableInstr.h
index 0ff10a56d4feb..67aba26a142bd 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.h
+++ b/llvm/utils/TableGen/X86RecognizableInstr.h
@@ -354,6 +354,11 @@ class RecognizableInstr : public RecognizableInstrBase {
};
std::string getMnemonic(const CodeGenInstruction *I, unsigned Variant);
+bool isRegisterOperand(const Record *Rec);
+bool isMemoryOperand(const Record *Rec);
+bool isImmediateOperand(const Record *Rec);
+unsigned getRegOperandSize(const Record *RegRec);
+unsigned getMemOperandSize(const Record *MemRec);
} // namespace X86Disassembler
} // namespace llvm
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