[llvm] dc68ca3 - [X86][tablgen] Rename field hasREX_WPrefix to hasREX_W for X86Inst. NFC
Shengchen Kan via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 26 08:21:05 PDT 2022
Author: Shengchen Kan
Date: 2022-03-26T23:14:08+08:00
New Revision: dc68ca3eff60d4fd067b2ba1ec4932f88b20a48e
URL: https://github.com/llvm/llvm-project/commit/dc68ca3eff60d4fd067b2ba1ec4932f88b20a48e
DIFF: https://github.com/llvm/llvm-project/commit/dc68ca3eff60d4fd067b2ba1ec4932f88b20a48e.diff
LOG: [X86][tablgen] Rename field hasREX_WPrefix to hasREX_W for X86Inst. NFC
To make it more like hasVEX_L and hasEVEX_K, etc.
Added:
Modified:
llvm/lib/Target/X86/X86InstrArithmetic.td
llvm/lib/Target/X86/X86InstrControl.td
llvm/lib/Target/X86/X86InstrFormats.td
llvm/utils/TableGen/X86FoldTablesEmitter.cpp
llvm/utils/TableGen/X86RecognizableInstr.cpp
llvm/utils/TableGen/X86RecognizableInstr.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td
index 8337d2b37383d..f08ecdf6afc93 100644
--- a/llvm/lib/Target/X86/X86InstrArithmetic.td
+++ b/llvm/lib/Target/X86/X86InstrArithmetic.td
@@ -541,7 +541,7 @@ class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
Operand immoperand, SDPatternOperator immoperator,
Operand imm8operand, SDPatternOperator imm8operator,
bit hasOddOpcode, OperandSize opSize,
- bit hasREX_WPrefix> {
+ bit hasREX_W> {
/// VT - This is the value type itself.
ValueType VT = vt;
@@ -596,9 +596,9 @@ class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
/// to Opsize16. i32 sets this to OpSize32.
OperandSize OpSize = opSize;
- /// HasREX_WPrefix - This bit is set to true if the instruction should have
+ /// HasREX_W - This bit is set to true if the instruction should have
/// the 0x40 REX prefix. This is set for i64 types.
- bit HasREX_WPrefix = hasREX_WPrefix;
+ bit HasREX_W = hasREX_W;
}
def invalid_node : SDNode<"<<invalid_node>>", SDTIntLeaf,[],"<<invalid_node>>">;
@@ -634,7 +634,7 @@ class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins,
// Infer instruction prefixes from type info.
let OpSize = typeinfo.OpSize;
- let hasREX_WPrefix = typeinfo.HasREX_WPrefix;
+ let hasREX_W = typeinfo.HasREX_W;
}
// BinOpRR - Instructions like "add reg, reg, reg".
diff --git a/llvm/lib/Target/X86/X86InstrControl.td b/llvm/lib/Target/X86/X86InstrControl.td
index 6d969962afffa..aa89a6f0ff9d5 100644
--- a/llvm/lib/Target/X86/X86InstrControl.td
+++ b/llvm/lib/Target/X86/X86InstrControl.td
@@ -147,7 +147,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
// Win64 wants indirect jumps leaving the function to have a REX_W prefix.
// These are switched from TAILJMPr/m64_REX in MCInstLower.
- let isCodeGenOnly = 1, hasREX_WPrefix = 1 in {
+ let isCodeGenOnly = 1, hasREX_W = 1 in {
def JMP64r_REX : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
"rex64 jmp{q}\t{*}$dst", []>, Sched<[WriteJump]>;
let mayLoad = 1 in
@@ -384,7 +384,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
[]>, Sched<[WriteJumpLd]>;
// Win64 wants indirect jumps leaving the function to have a REX_W prefix.
- let hasREX_WPrefix = 1 in {
+ let hasREX_W = 1 in {
def TAILJMPr64_REX : PseudoI<(outs), (ins ptr_rc_tailcall:$dst),
[]>, Sched<[WriteJump]>;
diff --git a/llvm/lib/Target/X86/X86InstrFormats.td b/llvm/lib/Target/X86/X86InstrFormats.td
index 0e7033fc233a0..3a44b4570e9b1 100644
--- a/llvm/lib/Target/X86/X86InstrFormats.td
+++ b/llvm/lib/Target/X86/X86InstrFormats.td
@@ -196,7 +196,7 @@ class OpSize32 { OperandSize OpSize = OpSize32; }
class AdSize16 { AddressSize AdSize = AdSize16; }
class AdSize32 { AddressSize AdSize = AdSize32; }
class AdSize64 { AddressSize AdSize = AdSize64; }
-class REX_W { bit hasREX_WPrefix = 1; }
+class REX_W { bit hasREX_W = 1; }
class LOCK { bit hasLockPrefix = 1; }
class REP { bit hasREPPrefix = 1; }
class TB { Map OpMap = TB; }
@@ -316,7 +316,7 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
bits<3> OpPrefixBits = OpPrefix.Value;
Map OpMap = OB; // Which opcode map does this inst have?
bits<4> OpMapBits = OpMap.Value;
- bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
+ bit hasREX_W = 0; // Does this inst require the REX.W prefix?
FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
Domain ExeDomain = d;
@@ -375,7 +375,7 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
// No need for 3rd bit, we don't need to distinguish NoPrfx from PS.
let TSFlags{12-11} = OpPrefixBits{1-0};
let TSFlags{16-13} = OpMapBits;
- let TSFlags{17} = hasREX_WPrefix;
+ let TSFlags{17} = hasREX_W;
let TSFlags{21-18} = ImmT.Value;
let TSFlags{24-22} = FPForm.Value;
let TSFlags{25} = hasLockPrefix;
diff --git a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
index 6fbef3f3a9eb9..f6391063d43c4 100644
--- a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
@@ -328,7 +328,7 @@ class IsMatch {
if (RegRI.Encoding != MemRI.Encoding || RegRI.Opcode != MemRI.Opcode ||
RegRI.OpPrefix != MemRI.OpPrefix || RegRI.OpMap != MemRI.OpMap ||
RegRI.OpSize != MemRI.OpSize || RegRI.AdSize != MemRI.AdSize ||
- RegRI.HasREX_WPrefix != MemRI.HasREX_WPrefix ||
+ RegRI.HasREX_W != MemRI.HasREX_W ||
RegRI.HasVEX_4V != MemRI.HasVEX_4V ||
RegRI.HasVEX_LPrefix != MemRI.HasVEX_LPrefix ||
RegRI.HasVEX_W != MemRI.HasVEX_W ||
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index 47d0d02133c56..879eadef3202f 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -85,7 +85,7 @@ RecognizableInstrBase::RecognizableInstrBase(const CodeGenInstruction &insn) {
Encoding = byteFromRec(Rec, "OpEncBits");
OpSize = byteFromRec(Rec, "OpSizeBits");
AdSize = byteFromRec(Rec, "AdSizeBits");
- HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
+ HasREX_W = Rec->getValueAsBit("hasREX_W");
HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
HasVEX_W = Rec->getValueAsBit("HasVEX_W");
IgnoresVEX_W = Rec->getValueAsBit("IgnoresVEX_W");
@@ -290,10 +290,10 @@ InstructionContext RecognizableInstr::insnContext() const {
errs() << "Instruction does not use a prefix: " << Name << "\n";
llvm_unreachable("Invalid prefix");
}
- } else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) {
- if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
+ } else if (Is64Bit || HasREX_W || AdSize == X86Local::AdSize64) {
+ if (HasREX_W && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
insnContext = IC_64BIT_REXW_OPSIZE;
- else if (HasREX_WPrefix && AdSize == X86Local::AdSize32)
+ else if (HasREX_W && AdSize == X86Local::AdSize32)
insnContext = IC_64BIT_REXW_ADSIZE;
else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
insnContext = IC_64BIT_XD_OPSIZE;
@@ -307,15 +307,15 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = IC_64BIT_OPSIZE;
else if (AdSize == X86Local::AdSize32)
insnContext = IC_64BIT_ADSIZE;
- else if (HasREX_WPrefix && OpPrefix == X86Local::XS)
+ else if (HasREX_W && OpPrefix == X86Local::XS)
insnContext = IC_64BIT_REXW_XS;
- else if (HasREX_WPrefix && OpPrefix == X86Local::XD)
+ else if (HasREX_W && OpPrefix == X86Local::XD)
insnContext = IC_64BIT_REXW_XD;
else if (OpPrefix == X86Local::XD)
insnContext = IC_64BIT_XD;
else if (OpPrefix == X86Local::XS)
insnContext = IC_64BIT_XS;
- else if (HasREX_WPrefix)
+ else if (HasREX_W)
insnContext = IC_64BIT_REXW;
else
insnContext = IC_64BIT;
@@ -390,7 +390,7 @@ void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
adjustOperandEncoding(encoding);
Spec->operands[operandIndex].encoding = encoding;
Spec->operands[operandIndex].type =
- typeFromString(std::string(typeName), HasREX_WPrefix, OpSize);
+ typeFromString(std::string(typeName), HasREX_W, OpSize);
++operandIndex;
++physicalOperandIndex;
@@ -855,9 +855,9 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
#define TYPE(str, type) if (s == str) return type;
OperandType RecognizableInstr::typeFromString(const std::string &s,
- bool hasREX_WPrefix,
+ bool hasREX_W,
uint8_t OpSize) {
- if(hasREX_WPrefix) {
+ if(hasREX_W) {
// For instructions with a REX_W prefix, a declared 32-bit register encoding
// is special.
TYPE("GR32", TYPE_R32)
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.h b/llvm/utils/TableGen/X86RecognizableInstr.h
index edb7dbf6aec29..27f344eb3d8d2 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.h
+++ b/llvm/utils/TableGen/X86RecognizableInstr.h
@@ -175,8 +175,8 @@ struct RecognizableInstrBase {
uint8_t OpSize;
/// The AdSize field from the record
uint8_t AdSize;
- /// The hasREX_WPrefix field from the record
- bool HasREX_WPrefix;
+ /// The hasREX_W field from the record
+ bool HasREX_W;
/// The hasVEX_4V field from the record
bool HasVEX_4V;
/// The HasVEX_WPrefix field from the record
@@ -247,7 +247,7 @@ class RecognizableInstr : public RecognizableInstrBase {
///
/// @param s - The string, as extracted by calling Rec->getName()
/// on a CodeGenInstruction::OperandInfo.
- /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
+ /// @param hasREX_W - Indicates whether the instruction has a REX.W
/// prefix. If it does, 32-bit register operands stay
/// 32-bit regardless of the operand size.
/// @param OpSize Indicates the operand size of the instruction.
@@ -255,7 +255,7 @@ class RecognizableInstr : public RecognizableInstrBase {
/// register sizes keep their size.
/// @return - The operand's type.
static OperandType typeFromString(const std::string& s,
- bool hasREX_WPrefix, uint8_t OpSize);
+ bool hasREX_W, uint8_t OpSize);
/// immediateEncodingFromString - Translates an immediate encoding from the
/// string provided in the LLVM tables to an OperandEncoding for use in
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