[llvm] c8ea732 - [X86][tablgen] Set ShouldBeEmitted to false when isAsmParserOnly is true. NFCI

[Shengchen Kan via llvm-commits]

Author: Shengchen Kan
Date: 2022-03-26T19:10:58+08:00
New Revision: c8ea7329377f5849205c775c78e5b00f9f52137f

URL: https://github.com/llvm/llvm-project/commit/c8ea7329377f5849205c775c78e5b00f9f52137f
DIFF: https://github.com/llvm/llvm-project/commit/c8ea7329377f5849205c775c78e5b00f9f52137f.diff

LOG: [X86][tablgen] Set ShouldBeEmitted to false when isAsmParserOnly is true. NFCI

In fact, an instruction can not be emitted to disassemble table when
`isAsmParserOnly` is true, so `isAsmParserOnly=true` implies
`ShouldBeEmitted=false`.

We check `isAsmParserOnly` in X86FoldTablesEmitter.cpp at a early stage
b/c none of them is foldable.

Added: 
    

Modified: 
    llvm/utils/TableGen/X86FoldTablesEmitter.cpp
    llvm/utils/TableGen/X86RecognizableInstr.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
index c5f5ed8e084dc..5b377a05d540b 100644
--- a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
@@ -344,9 +344,7 @@ class IsMatch {
         RegRec->getValueAsBit("hasNoTrackPrefix") !=
             MemRec->getValueAsBit("hasNoTrackPrefix") ||
         RegRec->getValueAsBit("EVEX_W1_VEX_W0") !=
-            MemRec->getValueAsBit("EVEX_W1_VEX_W0") ||
-        RegRec->getValueAsBit("isAsmParserOnly") !=
-            MemRec->getValueAsBit("isAsmParserOnly"))
+            MemRec->getValueAsBit("EVEX_W1_VEX_W0"))
       return false;
 
     // Make sure the sizes of the operands of both instructions suit each other.
@@ -556,10 +554,10 @@ void X86FoldTablesEmitter::run(formatted_raw_ostream &OS) {
       Target.getInstructionsByEnumValue();
 
   for (const CodeGenInstruction *Inst : NumberedInstructions) {
-    if (!Inst->TheDef->getNameInit() || !Inst->TheDef->isSubClassOf("X86Inst"))
-      continue;
-
     const Record *Rec = Inst->TheDef;
+    if (!Rec->getNameInit() || !Rec->isSubClassOf("X86Inst") ||
+        Rec->getValueAsBit("isAsmParserOnly"))
+      continue;
 
     // - Do not proceed if the instruction is marked as notMemoryFoldable.
     // - Instructions including RST register class operands are not relevant

diff  --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index 122074d411261..c2029d2693979 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -76,7 +76,9 @@ static uint8_t byteFromRec(const Record* rec, StringRef name) {
 }
 
 RecognizableInstrBase::RecognizableInstrBase(const CodeGenInstruction &insn)
-    : Rec(insn.TheDef), ShouldBeEmitted(Rec->isSubClassOf("X86Inst")) {
+    : Rec(insn.TheDef),
+      ShouldBeEmitted(Rec->isSubClassOf("X86Inst") &&
+                      !Rec->getValueAsBit("isAsmParserOnly")) {
   if (!ShouldBeEmitted)
     return;
 
@@ -134,10 +136,6 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables,
                                      const CodeGenInstruction &insn,
                                      InstrUID uid)
 {
-  // Ignore "asm parser only" instructions.
-  if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
-    return;
-
   RecognizableInstr recogInstr(tables, insn, uid);
 
   if (recogInstr.shouldBeEmitted()) {