[PATCH] D122475: [X86] Refactor X86ScalarSSEf16/32/64 with hasFP16/SSE1/SSE2. NFCI

[LuoYuanke via Phabricator via llvm-commits]

LuoYuanke added inline comments.


================
Comment at: llvm/lib/Target/X86/X86FastISel.cpp:521
   case MVT::f64:
-    if (X86ScalarSSEf32) {
+    if (HasSSE2) {
       if (IsNonTemporal && HasSSE4A)
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This fix a bug? Should previous code be X86ScalarSSEf64?


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:5669
 
+bool X86TargetLowering::hasBitPreservingFPLogic(EVT VT) const {
+  return VT == MVT::f32 || VT == MVT::f64 || VT.isVector() ||
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Just be curious. Why move those implementation from .h file?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D122475/new/

https://reviews.llvm.org/D122475