[PATCH] D122051: [RISCV] The immediate version of sgt/ugt lowering to slti/sltiu + xori

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:355
+// A 12-bit signed immediate sub one and exlcude zero
+def simm12_sub1_exc0 : PatLeaf<(imm), [{
+  if (!N->hasOneUse())
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Use `simm12_sub1_nonzero` that's consistent with `simm5_plus1_nonzero` from RISCVInstrInfoV.td


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Comment at: llvm/test/CodeGen/RISCV/i32-icmp.ll:1
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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Is there a similar test file for rv64?


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  https://reviews.llvm.org/D122051/new/

https://reviews.llvm.org/D122051