[llvm] 5975f1c - [AMDGPU][DOC][NFC] Added GFX1030 assembler syntax description
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 25 08:14:36 PDT 2022
Author: Dmitry Preobrazhensky
Date: 2022-03-25T18:14:04+03:00
New Revision: 5975f1c5f968e07b350d6279f173d68d36a80a50
URL: https://github.com/llvm/llvm-project/commit/5975f1c5f968e07b350d6279f173d68d36a80a50
DIFF: https://github.com/llvm/llvm-project/commit/5975f1c5f968e07b350d6279f173d68d36a80a50.diff
LOG: [AMDGPU][DOC][NFC] Added GFX1030 assembler syntax description
Added:
llvm/docs/AMDGPU/AMDGPUAsmGFX1030.rst
llvm/docs/AMDGPU/gfx1030_attr.rst
llvm/docs/AMDGPU/gfx1030_dst.rst
llvm/docs/AMDGPU/gfx1030_fx_operand.rst
llvm/docs/AMDGPU/gfx1030_hwreg.rst
llvm/docs/AMDGPU/gfx1030_imm16_73139a.rst
llvm/docs/AMDGPU/gfx1030_imm16_a04fb3.rst
llvm/docs/AMDGPU/gfx1030_label.rst
llvm/docs/AMDGPU/gfx1030_m_254bcb.rst
llvm/docs/AMDGPU/gfx1030_m_f5d306.rst
llvm/docs/AMDGPU/gfx1030_msg.rst
llvm/docs/AMDGPU/gfx1030_opt.rst
llvm/docs/AMDGPU/gfx1030_param.rst
llvm/docs/AMDGPU/gfx1030_saddr_9cd3cf.rst
llvm/docs/AMDGPU/gfx1030_saddr_beaa25.rst
llvm/docs/AMDGPU/gfx1030_saddr_d75725.rst
llvm/docs/AMDGPU/gfx1030_sbase_010ce0.rst
llvm/docs/AMDGPU/gfx1030_sbase_020892.rst
llvm/docs/AMDGPU/gfx1030_sdst_0804b1.rst
llvm/docs/AMDGPU/gfx1030_sdst_2e4c2a.rst
llvm/docs/AMDGPU/gfx1030_sdst_362c37.rst
llvm/docs/AMDGPU/gfx1030_sdst_3759f6.rst
llvm/docs/AMDGPU/gfx1030_sdst_386c33.rst
llvm/docs/AMDGPU/gfx1030_sdst_3bc700.rst
llvm/docs/AMDGPU/gfx1030_sdst_54e16e.rst
llvm/docs/AMDGPU/gfx1030_sdst_8078f5.rst
llvm/docs/AMDGPU/gfx1030_sdst_ea3f10.rst
llvm/docs/AMDGPU/gfx1030_simm32_6f0844.rst
llvm/docs/AMDGPU/gfx1030_simm32_a3e80c.rst
llvm/docs/AMDGPU/gfx1030_simm32_be0c1c.rst
llvm/docs/AMDGPU/gfx1030_soffset_59fade.rst
llvm/docs/AMDGPU/gfx1030_soffset_c40a5a.rst
llvm/docs/AMDGPU/gfx1030_soffset_fef808.rst
llvm/docs/AMDGPU/gfx1030_src_37d670.rst
llvm/docs/AMDGPU/gfx1030_src_516946.rst
llvm/docs/AMDGPU/gfx1030_src_823582.rst
llvm/docs/AMDGPU/gfx1030_src_c27036.rst
llvm/docs/AMDGPU/gfx1030_src_cf1cda.rst
llvm/docs/AMDGPU/gfx1030_src_d5cd94.rst
llvm/docs/AMDGPU/gfx1030_src_e0345d.rst
llvm/docs/AMDGPU/gfx1030_src_e9e6db.rst
llvm/docs/AMDGPU/gfx1030_srsrc_5dafbc.rst
llvm/docs/AMDGPU/gfx1030_srsrc_cf7132.rst
llvm/docs/AMDGPU/gfx1030_srsrc_e73d16.rst
llvm/docs/AMDGPU/gfx1030_ssamp.rst
llvm/docs/AMDGPU/gfx1030_ssrc_054e2a.rst
llvm/docs/AMDGPU/gfx1030_ssrc_2a042f.rst
llvm/docs/AMDGPU/gfx1030_ssrc_3ec588.rst
llvm/docs/AMDGPU/gfx1030_ssrc_460c63.rst
llvm/docs/AMDGPU/gfx1030_ssrc_48e8e7.rst
llvm/docs/AMDGPU/gfx1030_ssrc_6fbc49.rst
llvm/docs/AMDGPU/gfx1030_ssrc_7da351.rst
llvm/docs/AMDGPU/gfx1030_ssrc_81ba27.rst
llvm/docs/AMDGPU/gfx1030_ssrc_9a4448.rst
llvm/docs/AMDGPU/gfx1030_tgt.rst
llvm/docs/AMDGPU/gfx1030_type_deviation.rst
llvm/docs/AMDGPU/gfx1030_vaddr_373b95.rst
llvm/docs/AMDGPU/gfx1030_vaddr_49d53a.rst
llvm/docs/AMDGPU/gfx1030_vaddr_9aeece.rst
llvm/docs/AMDGPU/gfx1030_vaddr_9f7133.rst
llvm/docs/AMDGPU/gfx1030_vaddr_b73dc0.rst
llvm/docs/AMDGPU/gfx1030_vaddr_cdc744.rst
llvm/docs/AMDGPU/gfx1030_vaddr_f20ee4.rst
llvm/docs/AMDGPU/gfx1030_vcc.rst
llvm/docs/AMDGPU/gfx1030_vdata0_6802ce.rst
llvm/docs/AMDGPU/gfx1030_vdata0_fd235e.rst
llvm/docs/AMDGPU/gfx1030_vdata1_6802ce.rst
llvm/docs/AMDGPU/gfx1030_vdata1_fd235e.rst
llvm/docs/AMDGPU/gfx1030_vdata_15d255.rst
llvm/docs/AMDGPU/gfx1030_vdata_325b78.rst
llvm/docs/AMDGPU/gfx1030_vdata_4d8ecf.rst
llvm/docs/AMDGPU/gfx1030_vdata_56f215.rst
llvm/docs/AMDGPU/gfx1030_vdata_6802ce.rst
llvm/docs/AMDGPU/gfx1030_vdata_87fb90.rst
llvm/docs/AMDGPU/gfx1030_vdata_b2a787.rst
llvm/docs/AMDGPU/gfx1030_vdata_c08393.rst
llvm/docs/AMDGPU/gfx1030_vdata_c61803.rst
llvm/docs/AMDGPU/gfx1030_vdata_e016a1.rst
llvm/docs/AMDGPU/gfx1030_vdata_fd235e.rst
llvm/docs/AMDGPU/gfx1030_vdst_3d7dcf.rst
llvm/docs/AMDGPU/gfx1030_vdst_463513.rst
llvm/docs/AMDGPU/gfx1030_vdst_473a69.rst
llvm/docs/AMDGPU/gfx1030_vdst_48d3a8.rst
llvm/docs/AMDGPU/gfx1030_vdst_48e42f.rst
llvm/docs/AMDGPU/gfx1030_vdst_5d50a1.rst
llvm/docs/AMDGPU/gfx1030_vdst_69a144.rst
llvm/docs/AMDGPU/gfx1030_vdst_719833.rst
llvm/docs/AMDGPU/gfx1030_vdst_89680f.rst
llvm/docs/AMDGPU/gfx1030_vdst_a49b76.rst
llvm/docs/AMDGPU/gfx1030_vdst_bdb32f.rst
llvm/docs/AMDGPU/gfx1030_vdst_d0dc43.rst
llvm/docs/AMDGPU/gfx1030_vdst_d7c57e.rst
llvm/docs/AMDGPU/gfx1030_vdst_f47754.rst
llvm/docs/AMDGPU/gfx1030_vdst_f8490d.rst
llvm/docs/AMDGPU/gfx1030_vsrc_533a4e.rst
llvm/docs/AMDGPU/gfx1030_vsrc_6802ce.rst
llvm/docs/AMDGPU/gfx1030_vsrc_e016a1.rst
llvm/docs/AMDGPU/gfx1030_vsrc_fd235e.rst
llvm/docs/AMDGPU/gfx1030_waitcnt.rst
Modified:
llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst
llvm/docs/AMDGPU/AMDGPUAsmGFX1011.rst
llvm/docs/AMDGPUInstructionSyntax.rst
llvm/docs/AMDGPUUsage.rst
Removed:
################################################################################
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst
index 10b9fba128625..e4207084ee239 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst
@@ -6,7 +6,7 @@
**************************************************
====================================================================================
-Syntax of Core GFX10 Instructions
+Syntax of GFX10 RDNA1 Instructions
====================================================================================
.. contents::
@@ -15,7 +15,7 @@ Syntax of Core GFX10 Instructions
Introduction
============
-This document describes the syntax of *core* GFX10 instructions.
+This document describes the syntax of GFX10 RDNA1 (gfx1010) instructions.
Notation
========
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX1011.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX1011.rst
index 8180202950f82..23790479c1800 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX1011.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX1011.rst
@@ -17,7 +17,7 @@ Introduction
This document describes the syntax of *instructions specific to gfx1011 and gfx1012*.
-For a description of other gfx1011 and gfx1012 instructions see :doc:`Syntax of Core GFX10 Instructions<AMDGPUAsmGFX10>`.
+For a description of other gfx1011 and gfx1012 instructions see :doc:`Syntax of GFX10 RDNA1 Instructions<AMDGPUAsmGFX10>`.
Notation
========
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX1030.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX1030.rst
new file mode 100644
index 0000000000000..9079b42607ebe
--- /dev/null
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX1030.rst
@@ -0,0 +1,2166 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+====================================================================================
+Syntax of GFX10 RDNA2 Instructions
+====================================================================================
+
+.. contents::
+ :local:
+
+Introduction
+============
+
+This document describes the syntax of GFX10 RDNA2 instructions.
+
+GFX10 RDNA2 family includes gfx1030, gfx1031, gfx1032, gfx1033, gfx1034, gfx1035 and gfx1036 GPUs.
+
+Notation
+========
+
+Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
+
+Overview
+========
+
+An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
+
+Instructions
+============
+
+
+DPP16
+-----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_add_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_add_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_add_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_and_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ashrrev_i32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_bfrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ceil_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ceil_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cndmask_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cos_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cos_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f16_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f16_i16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f16_u16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_i32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_u32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_ubyte0_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_ubyte1_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_ubyte2_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_f32_ubyte3_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_flr_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_dot2c_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`f16x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`f16x2<amdgpu_synid_gfx1030_type_deviation>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_dot4c_i32_i8_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`i8x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`i8x4<amdgpu_synid_gfx1030_type_deviation>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_exp_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_exp_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ffbh_i32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ffbh_u32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ffbl_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_floor_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_floor_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_fmac_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_fmac_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_fract_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_fract_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_frexp_exp_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_frexp_exp_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_frexp_mant_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_frexp_mant_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_ldexp_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`i16<amdgpu_synid_gfx1030_type_deviation>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_log_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_log_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_lshlrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_lshrrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_max_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_max_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_max_i32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_max_u32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_min_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_min_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_min_i32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_min_u32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mov_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_movreld_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_movrels_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_movrelsd_2_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_movrelsd_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_hi_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_hi_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_legacy_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_mul_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_not_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_or_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rcp_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rcp_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rcp_iflag_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rndne_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rndne_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rsq_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_rsq_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sat_pk_u8_i16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`::ref:`u8x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sin_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sin_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sqrt_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sqrt_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sub_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sub_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sub_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_sub_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_subrev_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_subrev_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_subrev_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_subrev_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_trunc_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_xnor_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+ v_xor_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+
+DPP8
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_add_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_add_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_add_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_and_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ashrrev_i32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_bfrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ceil_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ceil_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cndmask_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cos_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cos_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f16_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f16_i16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f16_u16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_i32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_u32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_ubyte0_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_ubyte1_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_ubyte2_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_f32_ubyte3_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_flr_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_norm_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_off_f32_i4_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_rpi_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_u16_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_cvt_u32_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_dot2c_f32_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`f16x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`f16x2<amdgpu_synid_gfx1030_type_deviation>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_dot4c_i32_i8_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`i8x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`i8x4<amdgpu_synid_gfx1030_type_deviation>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_exp_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_exp_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ffbh_i32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ffbh_u32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ffbl_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_floor_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_floor_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_fmac_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_fmac_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_fract_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_fract_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_frexp_exp_i16_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_frexp_exp_i32_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_frexp_mant_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_frexp_mant_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_ldexp_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`i16<amdgpu_synid_gfx1030_type_deviation>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_log_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_log_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_lshlrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_lshrrev_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_max_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_max_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_max_i32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_max_u32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_min_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_min_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_min_i32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_min_u32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mov_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_movreld_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_movrels_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_movrelsd_2_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_movrelsd_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_hi_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_hi_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_i32_i24_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_legacy_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_mul_u32_u24_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_not_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_or_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rcp_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rcp_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rcp_iflag_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rndne_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rndne_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rsq_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_rsq_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sat_pk_u8_i16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`::ref:`u8x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sin_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sin_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sqrt_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sqrt_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sub_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sub_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sub_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_sub_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_subrev_co_ci_u32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_subrev_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_subrev_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_subrev_nc_u32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_trunc_f16_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_trunc_f32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_xnor_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+ v_xor_b32_dpp :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>` :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+
+DS
+--
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ ds_add_f32 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_rtn_u64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_u32 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_add_u64 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_b32 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_b64 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_rtn_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_and_rtn_b64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_append :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_bpermute_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>`
+ ds_cmpst_b32 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx1030_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_b64 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx1030_vdata0_fd235e>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_f32 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx1030_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_f64 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx1030_vdata0_fd235e>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx1030_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_b64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx1030_vdata0_fd235e>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx1030_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_cmpst_rtn_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx1030_vdata0_fd235e>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_condxchg32_rtn_b64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_consume :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_rtn_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_rtn_u64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_u32 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_dec_u64 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_barrier :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_init :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_br :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_p :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_release_all :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_gws_sema_v :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_rtn_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_rtn_u64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_u32 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_inc_u64 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_f32 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_f64 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_i32 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_i64 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_i32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_i64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_rtn_u64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_u32 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_max_u64 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_f32 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_f64 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_i32 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_i64 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_i32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_i64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_rtn_u64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_u32 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_min_u64 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_b32 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx1030_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_b64 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx1030_vdata0_fd235e>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_rtn_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx1030_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_mskor_rtn_b64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx1030_vdata0_fd235e>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_nop
+ ds_or_b32 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_b64 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_rtn_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_or_rtn_b64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_ordered_count :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_permute_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>`
+ ds_read2_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`::ref:`b32x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2_b64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_69a144>`::ref:`b64x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2st64_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`::ref:`b32x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read2st64_b64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_69a144>`::ref:`b64x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_addtid_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b128 :ref:`vdst<amdgpu_synid_gfx1030_vdst_69a144>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_b96 :ref:`vdst<amdgpu_synid_gfx1030_vdst_48e42f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_i8_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u16_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_read_u8_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_rtn_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_rtn_u64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_u32 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_rsub_u64 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_rtn_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_rtn_u64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_u32 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_sub_u64 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_swizzle_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>` :ref:`pattern<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrap_rtn_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx1030_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2_b32 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx1030_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2_b64 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx1030_vdata0_fd235e>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2st64_b32 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx1030_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write2st64_b64 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx1030_vdata0_fd235e>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_addtid_b32 :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b128 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b16 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b16_d16_hi :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b32 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b64 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b8 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b8_d16_hi :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_write_b96 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_56f215>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2_rtn_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`::ref:`b32x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx1030_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2_rtn_b64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_69a144>`::ref:`b64x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx1030_vdata0_fd235e>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2st64_rtn_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`::ref:`b32x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx1030_vdata0_6802ce>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_6802ce>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg2st64_rtn_b64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_69a144>`::ref:`b64x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx1030_vdata0_fd235e>`, :ref:`vdata1<amdgpu_synid_gfx1030_vdata1_fd235e>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg_rtn_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_wrxchg_rtn_b64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_b32 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_b64 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_rtn_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+ ds_xor_rtn_b64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
+
+EXP
+---
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ exp :ref:`tgt<amdgpu_synid_gfx1030_tgt>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_533a4e>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_533a4e>`, :ref:`vsrc2<amdgpu_synid_gfx1030_vsrc_533a4e>`, :ref:`vsrc3<amdgpu_synid_gfx1030_vsrc_533a4e>` :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
+
+FLAT
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ flat_atomic_add :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_and :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`b32x2<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>`::ref:`b64x2<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_dec :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_fcmpswap :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`f32x2<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_fcmpswap_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>`::ref:`f64x2<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_fmax :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_fmax_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_fmin :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_fmin_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_inc :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_or :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_smax :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_smin :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_sub :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_swap :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_umax :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_umin :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_xor :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_dword :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx1030_vdst_48e42f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx1030_vdst_69a144>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_sbyte :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_short_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_sshort :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_ubyte :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_load_ushort :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_byte :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_byte_d16_hi :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_dword :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_dwordx2 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_dwordx3 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_56f215>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_dwordx4 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_short :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ flat_store_short_d16_hi :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9f7133>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>` :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_add :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_add_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_and :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_and_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_cmpswap :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`b32x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>`::ref:`b64x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_csub :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_dec :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_dec_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_fcmpswap :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`f32x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_fcmpswap_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>`::ref:`f64x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_fmax :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_fmax_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_fmin :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_fmin_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_inc :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_inc_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_or :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_or_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_smax :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_smax_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_smin :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_smin_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_sub :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_sub_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_swap :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_swap_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_umax :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_umax_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_umin :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_umin_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_xor :ref:`vdst<amdgpu_synid_gfx1030_vdst_d0dc43>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_atomic_xor_x2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_463513>`::ref:`opt<amdgpu_synid_gfx1030_opt>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_dword :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_dword_addtid :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_9cd3cf>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx1030_vdst_48e42f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx1030_vdst_69a144>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_sbyte :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_short_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_sshort :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_ubyte :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_load_ushort :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_store_byte :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_store_byte_d16_hi :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_store_dword :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_store_dword_addtid :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_9cd3cf>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_store_dwordx2 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_store_dwordx3 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_56f215>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_store_dwordx4 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_store_short :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ global_store_short_d16_hi :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_dword :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx1030_vdst_48e42f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx1030_vdst_69a144>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_sbyte :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_short_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_sshort :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_ubyte :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_load_ushort :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_byte :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_byte_d16_hi :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_dword :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_dwordx2 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_dwordx3 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_56f215>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_dwordx4 :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_short :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ scratch_store_short_d16_hi :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>` :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+
+MIMG
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ image_atomic_add :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_and :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx1030_vdata_4d8ecf>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_dec :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_fcmpswap :ref:`vdata<amdgpu_synid_gfx1030_vdata_4d8ecf>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_fmax :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_fmin :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_inc :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_or :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_smax :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_smin :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_sub :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_swap :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_umax :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_umin :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_atomic_xor :ref:`vdata<amdgpu_synid_gfx1030_vdata_325b78>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_bvh64_intersect_ray :ref:`vdst<amdgpu_synid_gfx1030_vdst_f8490d>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_49d53a>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_5dafbc>` :ref:`a16<amdgpu_synid_a16>`
+ image_bvh_intersect_ray :ref:`vdst<amdgpu_synid_gfx1030_vdst_f8490d>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_49d53a>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_5dafbc>` :ref:`a16<amdgpu_synid_a16>`
+ image_gather4 :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b_cl :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b_cl_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_b_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b_cl :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b_cl_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_b_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_cl :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_cl_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_l :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_l_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_lz :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_lz_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_c_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_cl :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_cl_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_l :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_l_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_lz :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_lz_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_gather4_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_48d3a8>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_get_lod :ref:`vdst<amdgpu_synid_gfx1030_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_get_resinfo :ref:`vdst<amdgpu_synid_gfx1030_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_load :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_load_mip :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_load_mip_pck :ref:`vdst<amdgpu_synid_gfx1030_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_load_mip_pck_sgn :ref:`vdst<amdgpu_synid_gfx1030_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_load_pck :ref:`vdst<amdgpu_synid_gfx1030_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_load_pck_sgn :ref:`vdst<amdgpu_synid_gfx1030_vdst_3d7dcf>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_msaa_load :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_b :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_b_cl :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_b_cl_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_b_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_b :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_b_cl :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_b_cl_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_b_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_cl :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_cl_g16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_cl_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_cl_o_g16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_g16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cd_o_g16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cl :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_cl_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_cl :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_cl_g16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_cl_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_cl_o_g16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_g16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_d_o_g16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_l :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_l_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_lz :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_lz_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_c_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_cl :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_cl_g16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_cl_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_cl_o_g16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_g16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cd_o_g16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cl :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_cl_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_cl :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_cl_g16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_cl_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_cl_o_g16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_g16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_d_o_g16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_l :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_l_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_lz :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_lz_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_sample_o :ref:`vdst<amdgpu_synid_gfx1030_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>`, :ref:`ssamp<amdgpu_synid_gfx1030_ssamp>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_store :ref:`vdata<amdgpu_synid_gfx1030_vdata_15d255>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_store_mip :ref:`vdata<amdgpu_synid_gfx1030_vdata_15d255>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_store_mip_pck :ref:`vdata<amdgpu_synid_gfx1030_vdata_c08393>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+ image_store_pck :ref:`vdata<amdgpu_synid_gfx1030_vdata_c08393>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
+
+MTBUF
+-----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ tbuffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx1030_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx1030_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_x :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx1030_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx1030_vdst_a49b76>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx1030_vdst_f47754>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ tbuffer_store_format_d16_x :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_d16_xy :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_x :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx1030_vdata_56f215>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ tbuffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+
+MUBUF
+-----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ buffer_atomic_add :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_add_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_and :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_and_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_cmpswap :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`b32x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_cmpswap_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_87fb90>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`b64x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_csub :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_dec :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_dec_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fcmpswap :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`f32x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fcmpswap_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_87fb90>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`f64x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fmax :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fmax_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fmin :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_fmin_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`f64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_inc :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_inc_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_or :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_or_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smax :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smax_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smin :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_smin_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_sub :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_sub_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_swap :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_swap_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umax :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umax_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umin :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_umin_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_xor :ref:`vdata<amdgpu_synid_gfx1030_vdata_c61803>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_atomic_xor_x2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_b2a787>`::ref:`dst<amdgpu_synid_gfx1030_dst>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_gl0_inv
+ buffer_gl1_inv
+ buffer_load_dword :ref:`vdst<amdgpu_synid_gfx1030_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_dwordx2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_dwordx3 :ref:`vdst<amdgpu_synid_gfx1030_vdst_a49b76>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_dwordx4 :ref:`vdst<amdgpu_synid_gfx1030_vdst_f47754>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_d16_x :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_d16_xy :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid_gfx1030_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid_gfx1030_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_x :ref:`vdst<amdgpu_synid_gfx1030_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_format_xy :ref:`vdst<amdgpu_synid_gfx1030_vdst_d7c57e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_xyz :ref:`vdst<amdgpu_synid_gfx1030_vdst_a49b76>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_format_xyzw :ref:`vdst<amdgpu_synid_gfx1030_vdst_f47754>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_sbyte :ref:`vdst<amdgpu_synid_gfx1030_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_sbyte_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_short_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_short_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_sshort :ref:`vdst<amdgpu_synid_gfx1030_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_ubyte :ref:`vdst<amdgpu_synid_gfx1030_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_load_ubyte_d16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid_gfx1030_vdst_5d50a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+ buffer_load_ushort :ref:`vdst<amdgpu_synid_gfx1030_vdst_719833>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
+ buffer_store_byte :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_byte_d16_hi :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dword :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx2 :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx3 :ref:`vdata<amdgpu_synid_gfx1030_vdata_56f215>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_dwordx4 :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_x :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_xy :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_x :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xy :ref:`vdata<amdgpu_synid_gfx1030_vdata_fd235e>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xyz :ref:`vdata<amdgpu_synid_gfx1030_vdata_56f215>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_format_xyzw :ref:`vdata<amdgpu_synid_gfx1030_vdata_e016a1>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_short :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+ buffer_store_short_d16_hi :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_b73dc0>`, :ref:`srsrc<amdgpu_synid_gfx1030_srsrc_e73d16>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_fef808>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+
+SDWA
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add_co_ci_u32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_add_nc_u32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_and_b32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_ashrrev_i32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_bfrev_b32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ceil_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ceil_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cmp_class_f16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_class_f32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_i16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_i32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_u16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_eq_u32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_f16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_f32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_i32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_f_u32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_i16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_i32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_u16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ge_u32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_gt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_f16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_f32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_i16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_i32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_u16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_le_u32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_i16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_i32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_u16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_lt_u32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_i16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_i32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_u16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ne_u32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_neq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_neq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nge_f16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nge_f32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ngt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_ngt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nle_f16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nle_f32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlg_f16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlg_f32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlt_f16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_nlt_f32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_o_f16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_o_f32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_t_i32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_t_u32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_tru_f16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_tru_f32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_u_f16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmp_u_f32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_class_f16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_class_f32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_f16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_f32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_i16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_i32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_u16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_eq_u32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_f16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_f32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_i32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_f_u32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_f16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_f32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_i16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_i32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_u16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ge_u32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_f16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_f32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_i16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_i32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_u16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_gt_u32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_f16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_f32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_i16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_i32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_u16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_le_u32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lg_f16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lg_f32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_f16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_f32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_i16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_i32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_u16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_lt_u32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_i16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_i32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_u16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ne_u32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_neq_f16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_neq_f32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nge_f16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nge_f32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ngt_f16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_ngt_f32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nle_f16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nle_f32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlg_f16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlg_f32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlt_f16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_nlt_f32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_o_f16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_o_f32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_t_i32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_t_u32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_tru_f16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_tru_f32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_u_f16_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cmpx_u_f32_sdwa :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cndmask_b32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_cos_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cos_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f16_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f16_i16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f16_u16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_e0345d>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_i32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_u32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte0_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte1_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte2_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_f32_ubyte3_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_flr_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_norm_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_norm_u16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_off_f32_i4_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_rpi_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_u16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_cvt_u32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_exp_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_exp_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ffbh_i32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ffbh_u32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ffbl_b32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_floor_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_floor_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_fract_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_fract_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_exp_i16_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_exp_i32_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_mant_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_frexp_mant_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_ldexp_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`::ref:`i16<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_log_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_log_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_lshlrev_b32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_lshrrev_b32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_i32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_max_u32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_i32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_min_u32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mov_b32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_movreld_b32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_movrels_b32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_movrelsd_2_b32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_movrelsd_b32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_mul_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_hi_i32_i24_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_hi_u32_u24_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_i32_i24_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_legacy_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_mul_u32_u24_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_not_b32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_or_b32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_rcp_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rcp_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rcp_iflag_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rndne_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rndne_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rsq_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_rsq_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sat_pk_u8_i16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`::ref:`u8x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sin_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sin_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sqrt_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sqrt_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_sub_co_ci_u32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_sub_nc_u32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_co_ci_u32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_subrev_nc_u32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_trunc_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_trunc_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+ v_xnor_b32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+ v_xor_b32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>`, :ref:`src1<amdgpu_synid_gfx1030_src_37d670>`::ref:`m<amdgpu_synid_gfx1030_m_254bcb>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+
+SMEM
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_buffer_load_dword :ref:`sdst<amdgpu_synid_gfx1030_sdst_54e16e>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3bc700>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx1030_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx1030_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_010ce0>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_59fade>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_dcache_inv
+ s_gl1_inv
+ s_load_dword :ref:`sdst<amdgpu_synid_gfx1030_sdst_54e16e>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_load_dwordx16 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3bc700>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_load_dwordx2 :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_load_dwordx4 :ref:`sdst<amdgpu_synid_gfx1030_sdst_0804b1>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_load_dwordx8 :ref:`sdst<amdgpu_synid_gfx1030_sdst_362c37>`, :ref:`sbase<amdgpu_synid_gfx1030_sbase_020892>`, :ref:`soffset<amdgpu_synid_gfx1030_soffset_c40a5a>` :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
+ s_memrealtime :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`::ref:`b64<amdgpu_synid_gfx1030_type_deviation>`
+ s_memtime :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`::ref:`b64<amdgpu_synid_gfx1030_type_deviation>`
+
+SOP1
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_abs_i32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_and_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_and_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_andn1_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_andn1_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_andn1_wrexec_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_andn1_wrexec_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_andn2_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_andn2_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_andn2_wrexec_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_andn2_wrexec_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_bcnt0_i32_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_bcnt0_i32_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_bcnt1_i32_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_bcnt1_i32_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_bitreplicate_b64_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_bitset0_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_bitset0_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`
+ s_bitset1_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_bitset1_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`
+ s_brev_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_brev_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_cmov_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_cmov_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_ff0_i32_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_ff0_i32_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_ff1_i32_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_ff1_i32_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_flbit_i32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_flbit_i32_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_flbit_i32_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_flbit_i32_i64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_getpc_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`
+ s_mov_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_mov_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_movreld_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_movreld_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_movrels_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_6fbc49>`
+ s_movrels_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_81ba27>`
+ s_movrelsd_2_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_6fbc49>`
+ s_nand_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_nand_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_nor_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_nor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_not_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_not_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_or_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_or_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_orn1_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_orn1_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_orn2_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_orn2_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_quadmask_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_quadmask_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_rfe_b64 :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_81ba27>`
+ s_setpc_b64 :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_81ba27>`
+ s_sext_i32_i16 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_sext_i32_i8 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_swappc_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_81ba27>`
+ s_wqm_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_wqm_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_xnor_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_xnor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_xor_saveexec_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_54e16e>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_xor_saveexec_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_386c33>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_2a042f>`
+
+SOP2
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_abs
diff _i32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_add_i32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_add_u32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_addc_u32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_and_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_and_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_andn2_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_andn2_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_ashr_i32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`
+ s_ashr_i64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`
+ s_bfe_i32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`
+ s_bfe_i64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`
+ s_bfe_u32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_bfe_u64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`
+ s_bfm_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_bfm_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`
+ s_cselect_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_cselect_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_lshl1_add_u32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_lshl2_add_u32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_lshl3_add_u32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_lshl4_add_u32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_lshl_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`
+ s_lshl_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`
+ s_lshr_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`
+ s_lshr_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`
+ s_max_i32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_max_u32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_min_i32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_min_u32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_mul_hi_i32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_mul_hi_u32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_mul_i32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_nand_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_nand_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_nor_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_nor_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_or_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_or_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_orn2_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_orn2_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_pack_hh_b32_b16 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`
+ s_pack_lh_b32_b16 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`
+ s_pack_ll_b32_b16 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_sub_i32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_sub_u32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_subb_u32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_xnor_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_xnor_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_xor_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_xor_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_2a042f>`
+
+SOPC
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_bitcmp0_b32 :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_bitcmp0_b64 :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`
+ s_bitcmp1_b32 :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_bitcmp1_b64 :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`
+ s_cmp_eq_i32 :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_cmp_eq_u32 :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_cmp_eq_u64 :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_cmp_ge_i32 :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_cmp_ge_u32 :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_cmp_gt_i32 :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_cmp_gt_u32 :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_cmp_le_i32 :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_cmp_le_u32 :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_cmp_lg_i32 :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_cmp_lg_u32 :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_cmp_lg_u64 :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_2a042f>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_2a042f>`
+ s_cmp_lt_i32 :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+ s_cmp_lt_u32 :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_7da351>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_7da351>`
+
+SOPK
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_addk_i32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_call_b64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_ea3f10>`, :ref:`label<amdgpu_synid_gfx1030_label>`
+ s_cmovk_i32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_cmpk_eq_i32 :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_cmpk_eq_u32 :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx1030_imm16_a04fb3>`
+ s_cmpk_ge_i32 :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_cmpk_ge_u32 :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx1030_imm16_a04fb3>`
+ s_cmpk_gt_i32 :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_cmpk_gt_u32 :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx1030_imm16_a04fb3>`
+ s_cmpk_le_i32 :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_cmpk_le_u32 :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx1030_imm16_a04fb3>`
+ s_cmpk_lg_i32 :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_cmpk_lg_u32 :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx1030_imm16_a04fb3>`
+ s_cmpk_lt_i32 :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_cmpk_lt_u32 :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx1030_imm16_a04fb3>`
+ s_getreg_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`hwreg<amdgpu_synid_gfx1030_hwreg>`
+ s_movk_i32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_mulk_i32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_setreg_b32 :ref:`hwreg<amdgpu_synid_gfx1030_hwreg>`, :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_460c63>`
+ s_setreg_imm32_b32 :ref:`hwreg<amdgpu_synid_gfx1030_hwreg>`, :ref:`simm32<amdgpu_synid_gfx1030_simm32_a3e80c>`
+ s_subvector_loop_begin :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`label<amdgpu_synid_gfx1030_label>`
+ s_subvector_loop_end :ref:`sdst<amdgpu_synid_gfx1030_sdst_8078f5>`, :ref:`label<amdgpu_synid_gfx1030_label>`
+ s_version :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_waitcnt_expcnt :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_waitcnt_lgkmcnt :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_waitcnt_vmcnt :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_waitcnt_vscnt :ref:`ssrc<amdgpu_synid_gfx1030_ssrc_460c63>`, :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+
+SOPP
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **SRC**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ s_barrier
+ s_branch :ref:`label<amdgpu_synid_gfx1030_label>`
+ s_cbranch_cdbgsys :ref:`label<amdgpu_synid_gfx1030_label>`
+ s_cbranch_cdbgsys_and_user :ref:`label<amdgpu_synid_gfx1030_label>`
+ s_cbranch_cdbgsys_or_user :ref:`label<amdgpu_synid_gfx1030_label>`
+ s_cbranch_cdbguser :ref:`label<amdgpu_synid_gfx1030_label>`
+ s_cbranch_execnz :ref:`label<amdgpu_synid_gfx1030_label>`
+ s_cbranch_execz :ref:`label<amdgpu_synid_gfx1030_label>`
+ s_cbranch_scc0 :ref:`label<amdgpu_synid_gfx1030_label>`
+ s_cbranch_scc1 :ref:`label<amdgpu_synid_gfx1030_label>`
+ s_cbranch_vccnz :ref:`label<amdgpu_synid_gfx1030_label>`
+ s_cbranch_vccz :ref:`label<amdgpu_synid_gfx1030_label>`
+ s_clause :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_code_end
+ s_decperflevel :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_denorm_mode :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_endpgm
+ s_endpgm_ordered_ps_done
+ s_endpgm_saved
+ s_icache_inv
+ s_incperflevel :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_inst_prefetch :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_nop :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_round_mode :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_sendmsg :ref:`msg<amdgpu_synid_gfx1030_msg>`
+ s_sendmsghalt :ref:`msg<amdgpu_synid_gfx1030_msg>`
+ s_sethalt :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_setkill :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_setprio :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_sleep :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_trap :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_ttracedata
+ s_ttracedata_imm :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_waitcnt :ref:`waitcnt<amdgpu_synid_gfx1030_waitcnt>`
+ s_waitcnt_depctr :ref:`imm16<amdgpu_synid_gfx1030_imm16_73139a>`
+ s_wakeup
+
+VINTRP
+------
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_interp_mov_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`param<amdgpu_synid_gfx1030_param>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`attr<amdgpu_synid_gfx1030_attr>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`
+ v_interp_p1_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`attr<amdgpu_synid_gfx1030_attr>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`
+ v_interp_p2_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`attr<amdgpu_synid_gfx1030_attr>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`
+
+VOP1
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_bfrev_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_ceil_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_ceil_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_ceil_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_clrexcp
+ v_cos_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cos_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cvt_f16_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cvt_f16_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_e9e6db>`
+ v_cvt_f16_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_e9e6db>`
+ v_cvt_f32_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cvt_f32_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cvt_f32_i32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cvt_f32_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cvt_f32_ubyte0 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cvt_f32_ubyte1 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cvt_f32_ubyte2 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cvt_f32_ubyte3 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cvt_f64_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cvt_f64_i32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cvt_f64_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cvt_flr_i32_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cvt_i16_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cvt_i32_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cvt_i32_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cvt_norm_i16_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cvt_norm_u16_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cvt_off_f32_i4 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cvt_rpi_i32_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cvt_u16_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cvt_u32_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_cvt_u32_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_exp_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_exp_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_ffbh_i32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_ffbh_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_ffbl_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_floor_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_floor_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_floor_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_fract_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_fract_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_fract_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_frexp_exp_i16_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_frexp_exp_i32_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_frexp_exp_i32_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_frexp_mant_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_frexp_mant_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_frexp_mant_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_log_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_log_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_mov_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_movreld_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_movrels_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_movrelsd_2_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_movrelsd_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_nop
+ v_not_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_pipeflush
+ v_rcp_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_rcp_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_rcp_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_rcp_iflag_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_readfirstlane_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_2e4c2a>`, :ref:`src<amdgpu_synid_gfx1030_src_516946>`
+ v_rndne_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_rndne_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_rndne_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_rsq_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_rsq_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_rsq_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_sat_pk_u8_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`::ref:`u8x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_sin_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_sin_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_sqrt_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_sqrt_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_sqrt_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_swap_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_swaprel_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_trunc_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_trunc_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_trunc_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`
+
+VOP2
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add_co_ci_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>`
+ v_add_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_add_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_add_nc_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_and_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_ashrrev_i32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cndmask_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>`
+ v_cvt_pkrtz_f16_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`
+ v_dot2c_f32_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`f16x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`f16x2<amdgpu_synid_gfx1030_type_deviation>`
+ v_dot4c_i32_i8 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`i8x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`i8x4<amdgpu_synid_gfx1030_type_deviation>`
+ v_fmaak_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`simm32<amdgpu_synid_gfx1030_simm32_be0c1c>`
+ v_fmaak_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`simm32<amdgpu_synid_gfx1030_simm32_6f0844>`
+ v_fmac_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_fmac_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_fmac_legacy_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_fmamk_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`simm32<amdgpu_synid_gfx1030_simm32_be0c1c>`, :ref:`vsrc2<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_fmamk_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`simm32<amdgpu_synid_gfx1030_simm32_6f0844>`, :ref:`vsrc2<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_ldexp_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`i16<amdgpu_synid_gfx1030_type_deviation>`
+ v_lshlrev_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_lshrrev_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_max_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_max_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_max_i32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_max_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_min_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_min_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_min_i32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_min_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_mul_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_mul_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_mul_hi_i32_i24 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_mul_hi_u32_u24 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_mul_i32_i24 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_mul_legacy_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_mul_u32_u24 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_or_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_pk_fmac_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_sub_co_ci_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>`
+ v_sub_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_sub_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_sub_nc_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_subrev_co_ci_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>`
+ v_subrev_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_subrev_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_subrev_nc_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_xnor_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_xor_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+
+VOP3
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST0** **DST1** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_add3_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_add_co_ci_u32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`ssrc2<amdgpu_synid_gfx1030_ssrc_3ec588>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_co_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_add_lshl_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_add_nc_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_nc_i32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_nc_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_add_nc_u32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_alignbit_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_c27036>`::ref:`b16<amdgpu_synid_gfx1030_type_deviation>`
+ v_alignbyte_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_c27036>`::ref:`b16<amdgpu_synid_gfx1030_type_deviation>`
+ v_and_b32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_and_or_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_ashrrev_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_c27036>`::ref:`u16<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_ashrrev_i32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_ashrrev_i64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_bcnt_u32_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_bfe_i32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`
+ v_bfe_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_bfi_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_bfm_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_bfrev_b32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_ceil_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ceil_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ceil_f64_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_clrexcp_e64
+ v_cmp_class_f16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`
+ v_cmp_class_f32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`
+ v_cmp_class_f64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`
+ v_cmp_eq_f16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_f32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_f64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_eq_i16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmp_eq_i32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmp_eq_i64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmp_eq_u16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmp_eq_u32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmp_eq_u64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmp_f_f16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_f32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_f64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_f_i32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmp_f_i64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmp_f_u32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmp_f_u64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmp_ge_f16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_f32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_f64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ge_i16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmp_ge_i32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmp_ge_i64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmp_ge_u16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmp_ge_u32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmp_ge_u64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmp_gt_f16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_f32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_f64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_gt_i16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmp_gt_i32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmp_gt_i64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmp_gt_u16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmp_gt_u32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmp_gt_u64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmp_le_f16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_f32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_f64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_le_i16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmp_le_i32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmp_le_i64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmp_le_u16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmp_le_u32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmp_le_u64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmp_lg_f16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lg_f32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lg_f64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_f64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_lt_i16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmp_lt_i32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmp_lt_i64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmp_lt_u16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmp_lt_u32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmp_lt_u64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmp_ne_i16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmp_ne_i32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmp_ne_i64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmp_ne_u16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmp_ne_u32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmp_ne_u64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmp_neq_f16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_neq_f32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_neq_f64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nge_f64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_ngt_f64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nle_f64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlg_f64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_nlt_f64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_o_f64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_t_i32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmp_t_i64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmp_t_u32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmp_t_u64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmp_tru_f16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_tru_f32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_tru_f64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f16_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f32_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmp_u_f64_e64 :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_class_f16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`
+ v_cmpx_class_f32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`
+ v_cmpx_class_f64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`
+ v_cmpx_eq_f16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_f32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_f64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_eq_i16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmpx_eq_i32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmpx_eq_i64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmpx_eq_u16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmpx_eq_u32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmpx_eq_u64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmpx_f_f16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_f32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_f64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_f_i32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmpx_f_i64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmpx_f_u32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmpx_f_u64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmpx_ge_f16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_f32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_f64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ge_i16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmpx_ge_i32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmpx_ge_i64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmpx_ge_u16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmpx_ge_u32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmpx_ge_u64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmpx_gt_f16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_f32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_f64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_gt_i16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmpx_gt_i32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmpx_gt_i64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmpx_gt_u16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmpx_gt_u32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmpx_gt_u64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmpx_le_f16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_f32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_f64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_le_i16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmpx_le_i32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmpx_le_i64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmpx_le_u16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmpx_le_u32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmpx_le_u64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmpx_lg_f16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lg_f32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lg_f64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_f64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_lt_i16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmpx_lt_i32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmpx_lt_i64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmpx_lt_u16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmpx_lt_u32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmpx_lt_u64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmpx_ne_i16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmpx_ne_i32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmpx_ne_i64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmpx_ne_u16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_cmpx_ne_u32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmpx_ne_u64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmpx_neq_f16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_neq_f32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_neq_f64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nge_f64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_ngt_f64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nle_f64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlg_f64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_nlt_f64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_o_f64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_t_i32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmpx_t_i64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmpx_t_u32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_cmpx_t_u64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_cmpx_tru_f16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_tru_f32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_tru_f64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f16_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f32_e64 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cmpx_u_f64_e64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cndmask_b32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`ssrc2<amdgpu_synid_gfx1030_ssrc_3ec588>`
+ v_cos_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cos_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubeid_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubema_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubesc_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cubetc_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_i16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_e9e6db>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f16_u16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_e9e6db>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_f64_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_i32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_u32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte0_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte1_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte2_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f32_ubyte3_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_i32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_f64_u32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_flr_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`
+ v_cvt_i16_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_i32_f64_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_norm_i16_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_norm_u16_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_off_f32_i4_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_cvt_pk_i16_i32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>`
+ v_cvt_pk_u16_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`
+ v_cvt_pk_u8_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`
+ v_cvt_pknorm_i16_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`f16<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`f16<amdgpu_synid_gfx1030_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_cvt_pknorm_i16_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`
+ v_cvt_pknorm_u16_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`f16<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`f16<amdgpu_synid_gfx1030_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_cvt_pknorm_u16_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`
+ v_cvt_pkrtz_f16_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_rpi_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`
+ v_cvt_u16_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_u32_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_cvt_u32_f64_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_div_fixup_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_div_fixup_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fixup_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fmas_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_fmas_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_div_scale_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_div_scale_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`src2<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_exp_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_exp_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ffbh_i32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_ffbh_u32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_ffbl_b32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_floor_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_floor_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_floor_f64_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fma_legacy_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fmac_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fmac_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fmac_legacy_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fract_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fract_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_fract_f64_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_frexp_exp_i16_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`
+ v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`
+ v_frexp_exp_i32_f64_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`
+ v_frexp_mant_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_frexp_mant_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_frexp_mant_f64_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_mov_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`param<amdgpu_synid_gfx1030_param>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`attr<amdgpu_synid_gfx1030_attr>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_p1_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`attr<amdgpu_synid_gfx1030_attr>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_p1ll_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`attr<amdgpu_synid_gfx1030_attr>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_p1lv_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`attr<amdgpu_synid_gfx1030_attr>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`f16x2<amdgpu_synid_gfx1030_type_deviation>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_interp_p2_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`attr<amdgpu_synid_gfx1030_attr>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>` :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_interp_p2_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`attr<amdgpu_synid_gfx1030_attr>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`i16<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_ldexp_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lerp_u8 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`
+ v_log_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_log_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_lshl_add_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_lshl_or_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_lshlrev_b16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_c27036>`::ref:`u16<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_lshlrev_b32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_lshlrev_b64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_lshrrev_b16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_c27036>`::ref:`u16<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_lshrrev_b32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_lshrrev_b64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`
+ v_mad_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`, :ref:`src2<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i32_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i32_i24 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_i64_i32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`i64<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`, :ref:`src2<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u32_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u32_u24 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mad_u64_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`u64<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max3_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_max3_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max3_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`, :ref:`src2<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_max3_i32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_max3_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`, :ref:`src2<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_max3_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_max_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_max_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_max_i32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_max_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_max_u32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_mbcnt_hi_u32_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_mbcnt_lo_u32_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_med3_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_med3_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_med3_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`, :ref:`src2<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_med3_i32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_med3_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`, :ref:`src2<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_med3_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_min3_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_min3_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min3_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`, :ref:`src2<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_min3_i32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_min3_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`, :ref:`src2<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_min3_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_min_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_min_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_min_i32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_min_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_min_u32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_mov_b32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_movreld_b32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_movrels_b32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_movrelsd_2_b32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_movrelsd_b32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_mqsad_pk_u16_u8 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`::ref:`u16x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`u8x8<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u8x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src2<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`u16x4<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mqsad_u32_u8 :ref:`vdst<amdgpu_synid_gfx1030_vdst_69a144>`::ref:`u32x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`u8x8<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u8x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`vsrc2<amdgpu_synid_gfx1030_vsrc_e016a1>`::ref:`u32x4<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_msad_u8 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mul_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_hi_i32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_mul_hi_i32_i24_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_mul_hi_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_mul_hi_u32_u24_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_mul_i32_i24_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mul_legacy_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_mul_lo_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`
+ v_mul_lo_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_mul_u32_u24_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_mullit_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_nop_e64
+ v_not_b32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_or3_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_or_b32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_pack_b32_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+ v_perm_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_permlane16_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_9a4448>`, :ref:`ssrc2<amdgpu_synid_gfx1030_ssrc_9a4448>` :ref:`dpp_op_sel<amdgpu_synid_dpp_op_sel>`
+ v_permlanex16_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vdata<amdgpu_synid_gfx1030_vdata_6802ce>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_9a4448>`, :ref:`ssrc2<amdgpu_synid_gfx1030_ssrc_9a4448>` :ref:`dpp_op_sel<amdgpu_synid_dpp_op_sel>`
+ v_pipeflush_e64
+ v_qsad_pk_u16_u8 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`::ref:`u16x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`u8x8<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u8x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src2<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`u16x4<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_rcp_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_f64_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rcp_iflag_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_readlane_b32 :ref:`sdst<amdgpu_synid_gfx1030_sdst_2e4c2a>`, :ref:`src0<amdgpu_synid_gfx1030_src_516946>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_48e8e7>`
+ v_rndne_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rndne_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rndne_f64_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_rsq_f64_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sad_hi_u8 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`u8x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u8x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`u16x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u16x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sad_u8 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`u8x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u8x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sat_pk_u8_i16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`::ref:`u8x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`
+ v_sin_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sin_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sqrt_f64_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_co_ci_u32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`ssrc2<amdgpu_synid_gfx1030_ssrc_3ec588>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_co_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_sub_nc_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_nc_i32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_nc_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_sub_nc_u32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_co_ci_u32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`ssrc2<amdgpu_synid_gfx1030_ssrc_3ec588>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_co_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`sdst<amdgpu_synid_gfx1030_sdst_3759f6>`, :ref:`src0<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_subrev_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_subrev_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_subrev_nc_u32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_trig_preop_f64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f16_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_trunc_f64_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_bdb32f>`, :ref:`src<amdgpu_synid_gfx1030_src_d5cd94>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+ v_writelane_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`ssrc0<amdgpu_synid_gfx1030_ssrc_054e2a>`, :ref:`ssrc1<amdgpu_synid_gfx1030_ssrc_48e8e7>`
+ v_xad_u32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_xnor_b32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_xor3_b32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`
+ v_xor_b32_e64 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`
+
+VOP3P
+-----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_dot2_f32_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`f16x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`f16x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`f32<amdgpu_synid_gfx1030_type_deviation>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_dot2_i32_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`::ref:`i16x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`::ref:`i16x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_dot2_u32_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`::ref:`u16x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`::ref:`u16x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_dot4_i32_i8 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`i8x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`i8x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_dot4_u32_u8 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`u8x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u8x4<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_dot8_i32_i4 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`i4x8<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`i4x8<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`i32<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_dot8_u32_u4 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`u4x8<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u4x8<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`u32<amdgpu_synid_gfx1030_type_deviation>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_mix_f32 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`fx<amdgpu_synid_gfx1030_fx_operand>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`fx<amdgpu_synid_gfx1030_fx_operand>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`fx<amdgpu_synid_gfx1030_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_mixhi_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`fx<amdgpu_synid_gfx1030_fx_operand>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`fx<amdgpu_synid_gfx1030_fx_operand>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`fx<amdgpu_synid_gfx1030_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_fma_mixlo_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`fx<amdgpu_synid_gfx1030_fx_operand>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`fx<amdgpu_synid_gfx1030_fx_operand>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>`::ref:`m<amdgpu_synid_gfx1030_m_f5d306>`::ref:`fx<amdgpu_synid_gfx1030_fx_operand>` :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_add_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_ashrrev_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_c27036>`::ref:`u16x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_fma_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>`, :ref:`src2<amdgpu_synid_gfx1030_src_cf1cda>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_lshlrev_b16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_c27036>`::ref:`u16x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_lshrrev_b16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_c27036>`::ref:`u16x2<amdgpu_synid_gfx1030_type_deviation>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_mad_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`, :ref:`src2<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_mad_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>`, :ref:`src2<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_max_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_max_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_max_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_min_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_min_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_min_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_mul_f16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`src1<amdgpu_synid_gfx1030_src_cf1cda>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_mul_lo_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+ v_pk_sub_i16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+ v_pk_sub_u16 :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`src1<amdgpu_synid_gfx1030_src_c27036>` :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+
+VOPC
+----
+
+.. parsed-literal::
+
+ **INSTRUCTION** **DST** **SRC0** **SRC1**
+ \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+ v_cmp_class_f16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`
+ v_cmp_class_f32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`
+ v_cmp_class_f64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`
+ v_cmp_eq_f16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_eq_f32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_eq_f64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_eq_i16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_eq_i32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_eq_i64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_eq_u16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_eq_u32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_eq_u64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_f_f16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_f_f32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_f_f64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_f_i32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_f_i64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_f_u32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_f_u64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_ge_f16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_ge_f32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_ge_f64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_ge_i16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_ge_i32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_ge_i64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_ge_u16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_ge_u32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_ge_u64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_gt_f16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_gt_f32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_gt_f64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_gt_i16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_gt_i32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_gt_i64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_gt_u16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_gt_u32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_gt_u64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_le_f16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_le_f32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_le_f64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_le_i16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_le_i32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_le_i64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_le_u16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_le_u32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_le_u64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_lg_f16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_lg_f32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_lg_f64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_lt_f16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_lt_f32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_lt_f64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_lt_i16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_lt_i32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_lt_i64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_lt_u16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_lt_u32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_lt_u64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_ne_i16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_ne_i32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_ne_i64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_ne_u16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_ne_u32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_ne_u64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_neq_f16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_neq_f32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_neq_f64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_nge_f16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_nge_f32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_nge_f64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_ngt_f16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_ngt_f32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_ngt_f64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_nle_f16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_nle_f32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_nle_f64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_nlg_f16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_nlg_f32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_nlg_f64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_nlt_f16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_nlt_f32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_nlt_f64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_o_f16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_o_f32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_o_f64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_t_i32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_t_i64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_t_u32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_t_u64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_tru_f16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_tru_f32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_tru_f64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmp_u_f16 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_u_f32 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmp_u_f64 :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_class_f16 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`
+ v_cmpx_class_f32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`
+ v_cmpx_class_f64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`::ref:`b32<amdgpu_synid_gfx1030_type_deviation>`
+ v_cmpx_eq_f16 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_eq_f32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_eq_f64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_eq_i16 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_eq_i32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_eq_i64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_eq_u16 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_eq_u32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_eq_u64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_f_f16 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_f_f32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_f_f64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_f_i32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_f_i64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_f_u32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_f_u64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_ge_f16 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_ge_f32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_ge_f64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_ge_i16 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_ge_i32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_ge_i64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_ge_u16 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_ge_u32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_ge_u64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_gt_f16 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_gt_f32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_gt_f64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_gt_i16 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_gt_i32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_gt_i64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_gt_u16 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_gt_u32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_gt_u64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_le_f16 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_le_f32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_le_f64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_le_i16 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_le_i32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_le_i64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_le_u16 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_le_u32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_le_u64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_lg_f16 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_lg_f32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_lg_f64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_lt_f16 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_lt_f32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_lt_f64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_lt_i16 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_lt_i32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_lt_i64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_lt_u16 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_lt_u32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_lt_u64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_ne_i16 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_ne_i32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_ne_i64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_ne_u16 :ref:`src0<amdgpu_synid_gfx1030_src_e9e6db>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_ne_u32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_ne_u64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_neq_f16 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_neq_f32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_neq_f64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_nge_f16 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_nge_f32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_nge_f64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_ngt_f16 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_ngt_f32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_ngt_f64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_nle_f16 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_nle_f32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_nle_f64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_nlg_f16 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_nlg_f32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_nlg_f64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_nlt_f16 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_nlt_f32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_nlt_f64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_o_f16 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_o_f32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_o_f64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_t_i32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_t_i64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_t_u32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_t_u64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_tru_f16 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_tru_f32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_tru_f64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+ v_cmpx_u_f16 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_u_f32 :ref:`src0<amdgpu_synid_gfx1030_src_823582>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_6802ce>`
+ v_cmpx_u_f64 :ref:`src0<amdgpu_synid_gfx1030_src_d5cd94>`, :ref:`vsrc1<amdgpu_synid_gfx1030_vsrc_fd235e>`
+
+.. |---| unicode:: U+02014 .. em dash
+
+.. toctree::
+ :hidden:
+
+ gfx1030_attr
+ gfx1030_dst
+ gfx1030_fx_operand
+ gfx1030_hwreg
+ gfx1030_imm16_73139a
+ gfx1030_imm16_a04fb3
+ gfx1030_label
+ gfx1030_m_254bcb
+ gfx1030_m_f5d306
+ gfx1030_msg
+ gfx1030_opt
+ gfx1030_param
+ gfx1030_saddr_9cd3cf
+ gfx1030_saddr_beaa25
+ gfx1030_saddr_d75725
+ gfx1030_sbase_010ce0
+ gfx1030_sbase_020892
+ gfx1030_sdst_0804b1
+ gfx1030_sdst_2e4c2a
+ gfx1030_sdst_362c37
+ gfx1030_sdst_3759f6
+ gfx1030_sdst_386c33
+ gfx1030_sdst_3bc700
+ gfx1030_sdst_54e16e
+ gfx1030_sdst_8078f5
+ gfx1030_sdst_ea3f10
+ gfx1030_simm32_6f0844
+ gfx1030_simm32_a3e80c
+ gfx1030_simm32_be0c1c
+ gfx1030_soffset_59fade
+ gfx1030_soffset_c40a5a
+ gfx1030_soffset_fef808
+ gfx1030_src_37d670
+ gfx1030_src_516946
+ gfx1030_src_823582
+ gfx1030_src_c27036
+ gfx1030_src_cf1cda
+ gfx1030_src_d5cd94
+ gfx1030_src_e0345d
+ gfx1030_src_e9e6db
+ gfx1030_srsrc_5dafbc
+ gfx1030_srsrc_cf7132
+ gfx1030_srsrc_e73d16
+ gfx1030_ssamp
+ gfx1030_ssrc_054e2a
+ gfx1030_ssrc_2a042f
+ gfx1030_ssrc_3ec588
+ gfx1030_ssrc_460c63
+ gfx1030_ssrc_48e8e7
+ gfx1030_ssrc_6fbc49
+ gfx1030_ssrc_7da351
+ gfx1030_ssrc_81ba27
+ gfx1030_ssrc_9a4448
+ gfx1030_tgt
+ gfx1030_type_deviation
+ gfx1030_vaddr_373b95
+ gfx1030_vaddr_49d53a
+ gfx1030_vaddr_9aeece
+ gfx1030_vaddr_9f7133
+ gfx1030_vaddr_b73dc0
+ gfx1030_vaddr_cdc744
+ gfx1030_vaddr_f20ee4
+ gfx1030_vcc
+ gfx1030_vdata0_6802ce
+ gfx1030_vdata0_fd235e
+ gfx1030_vdata1_6802ce
+ gfx1030_vdata1_fd235e
+ gfx1030_vdata_15d255
+ gfx1030_vdata_325b78
+ gfx1030_vdata_4d8ecf
+ gfx1030_vdata_56f215
+ gfx1030_vdata_6802ce
+ gfx1030_vdata_87fb90
+ gfx1030_vdata_b2a787
+ gfx1030_vdata_c08393
+ gfx1030_vdata_c61803
+ gfx1030_vdata_e016a1
+ gfx1030_vdata_fd235e
+ gfx1030_vdst_3d7dcf
+ gfx1030_vdst_463513
+ gfx1030_vdst_473a69
+ gfx1030_vdst_48d3a8
+ gfx1030_vdst_48e42f
+ gfx1030_vdst_5d50a1
+ gfx1030_vdst_69a144
+ gfx1030_vdst_719833
+ gfx1030_vdst_89680f
+ gfx1030_vdst_a49b76
+ gfx1030_vdst_bdb32f
+ gfx1030_vdst_d0dc43
+ gfx1030_vdst_d7c57e
+ gfx1030_vdst_f47754
+ gfx1030_vdst_f8490d
+ gfx1030_vsrc_533a4e
+ gfx1030_vsrc_6802ce
+ gfx1030_vsrc_e016a1
+ gfx1030_vsrc_fd235e
+ gfx1030_waitcnt
diff --git a/llvm/docs/AMDGPU/gfx1030_attr.rst b/llvm/docs/AMDGPU/gfx1030_attr.rst
new file mode 100644
index 0000000000000..f8222f90f8a20
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_attr.rst
@@ -0,0 +1,29 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_attr:
+
+attr
+====
+
+Interpolation attribute and channel:
+
+ ============== ===================================
+ Syntax Description
+ ============== ===================================
+ attr{0..32}.x Attribute 0..32 with *x* channel.
+ attr{0..32}.y Attribute 0..32 with *y* channel.
+ attr{0..32}.z Attribute 0..32 with *z* channel.
+ attr{0..32}.w Attribute 0..32 with *w* channel.
+ ============== ===================================
+
+Examples:
+
+.. parsed-literal::
+
+ v_interp_p1_f32 v1, v0, attr0.x
+ v_interp_p1_f32 v1, v0, attr32.w
diff --git a/llvm/docs/AMDGPU/gfx1030_dst.rst b/llvm/docs/AMDGPU/gfx1030_dst.rst
new file mode 100644
index 0000000000000..4339de5cc7724
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_dst.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_dst:
+
+dst
+===
+
+This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.
diff --git a/llvm/docs/AMDGPU/gfx1030_fx_operand.rst b/llvm/docs/AMDGPU/gfx1030_fx_operand.rst
new file mode 100644
index 0000000000000..b6341a8b26e76
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_fx_operand.rst
@@ -0,0 +1,16 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_fx_operand:
+
+FX Operand
+==========
+
+This is an *f32* or *f16* operand depending on instruction modifiers:
+
+* Operand size is controlled by :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
+* Location of 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.
diff --git a/llvm/docs/AMDGPU/gfx1030_hwreg.rst b/llvm/docs/AMDGPU/gfx1030_hwreg.rst
new file mode 100644
index 0000000000000..2bf0904d55f45
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_hwreg.rst
@@ -0,0 +1,82 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_hwreg:
+
+hwreg
+=====
+
+Bits of a hardware register being accessed.
+
+The bits of this operand have the following meaning:
+
+ ======= ===================== ============
+ Bits Description Value Range
+ ======= ===================== ============
+ 5:0 Register *id*. 0..63
+ 10:6 First bit *offset*. 0..31
+ 15:11 *Size* in bits. 1..32
+ ======= ===================== ============
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
+* An *hwreg* value described below.
+
+ ==================================== ============================================================================
+ Hwreg Value Syntax Description
+ ==================================== ============================================================================
+ hwreg({0..63}) All bits of a register indicated by its *id*.
+ hwreg(<*name*>) All bits of a register indicated by its *name*.
+ hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by register *id*, first bit *offset* and *size*.
+ hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*.
+ ==================================== ============================================================================
+
+Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
+or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+
+Defined register *names* include:
+
+ ==================== ==========================================
+ Name Description
+ ==================== ==========================================
+ HW_REG_MODE Shader writeable mode bits.
+ HW_REG_STATUS Shader read-only status.
+ HW_REG_TRAPSTS Trap status.
+ HW_REG_HW_ID1 Id of wave, simd, compute unit, etc.
+ HW_REG_HW_ID2 Id of queue, pipeline, etc.
+ HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
+ HW_REG_LDS_ALLOC Per-wave LDS allocation.
+ HW_REG_IB_STS Counters of outstanding instructions.
+ HW_REG_SH_MEM_BASES Memory aperture.
+ HW_REG_TBA_LO tba_lo register.
+ HW_REG_TBA_HI tba_hi register.
+ HW_REG_TMA_LO tma_lo register.
+ HW_REG_TMA_HI tma_hi register.
+ HW_REG_FLAT_SCR_LO flat_scratch_lo register.
+ HW_REG_FLAT_SCR_HI flat_scratch_hi register.
+ HW_REG_POPS_PACKER pops_packer register.
+ HW_REG_SHADER_CYCLES Current graphics clock counter value.
+ ==================== ==========================================
+
+Examples:
+
+.. parsed-literal::
+
+ reg = 1
+ offset = 2
+ size = 4
+ hwreg_enc = reg | (offset << 6) | ((size - 1) << 11)
+
+ s_getreg_b32 s2, 0x1881
+ s_getreg_b32 s2, hwreg_enc // the same as above
+ s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above
+ s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above
+
+ s_getreg_b32 s2, hwreg(15)
+ s_getreg_b32 s2, hwreg(51, 1, 31)
+ s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
diff --git a/llvm/docs/AMDGPU/gfx1030_imm16_73139a.rst b/llvm/docs/AMDGPU/gfx1030_imm16_73139a.rst
new file mode 100644
index 0000000000000..e15457fa6903b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_imm16_73139a.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_imm16_73139a:
+
+imm16
+=====
+
+An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
diff --git a/llvm/docs/AMDGPU/gfx1030_imm16_a04fb3.rst b/llvm/docs/AMDGPU/gfx1030_imm16_a04fb3.rst
new file mode 100644
index 0000000000000..988c3b98f976f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_imm16_a04fb3.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_imm16_a04fb3:
+
+imm16
+=====
+
+An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535.
diff --git a/llvm/docs/AMDGPU/gfx1030_label.rst b/llvm/docs/AMDGPU/gfx1030_label.rst
new file mode 100644
index 0000000000000..31952a46dbf9d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_label.rst
@@ -0,0 +1,36 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_label:
+
+label
+=====
+
+A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
+* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
+
+Examples:
+
+.. parsed-literal::
+
+ offset = 30
+ label_1:
+ label_2 = . + 4
+
+ s_branch 32
+ s_branch offset + 2
+ s_branch label_1
+ s_branch label_2
+ s_branch label_3
+ s_branch label_4
+
+ label_3 = label_2 + 4
+ label_4:
diff --git a/llvm/docs/AMDGPU/gfx1030_m_254bcb.rst b/llvm/docs/AMDGPU/gfx1030_m_254bcb.rst
new file mode 100644
index 0000000000000..b187cc3044f1c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_m_254bcb.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_m_254bcb:
+
+m
+=
+
+This operand may be used with integer operand modifier :ref:`sext<amdgpu_synid_sext>`.
diff --git a/llvm/docs/AMDGPU/gfx1030_m_f5d306.rst b/llvm/docs/AMDGPU/gfx1030_m_f5d306.rst
new file mode 100644
index 0000000000000..69d62f68401e6
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_m_f5d306.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_m_f5d306:
+
+m
+=
+
+This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
diff --git a/llvm/docs/AMDGPU/gfx1030_msg.rst b/llvm/docs/AMDGPU/gfx1030_msg.rst
new file mode 100644
index 0000000000000..3f4a33c55a92f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_msg.rst
@@ -0,0 +1,100 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_msg:
+
+msg
+===
+
+A 16-bit message code. The bits of this operand have the following meaning:
+
+ ============ =============================== ===============
+ Bits Description Value Range
+ ============ =============================== ===============
+ 3:0 Message *type*. 0..15
+ 6:4 Optional *operation*. 0..7
+ 7:7 Unused. \-
+ 9:8 Optional *stream*. 0..3
+ 15:10 Unused. \-
+ ============ =============================== ===============
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
+* A *sendmsg* value described below.
+
+ ==================================== ====================================================
+ Sendmsg Value Syntax Description
+ ==================================== ====================================================
+ sendmsg(<*type*>) A message identified by its *type*.
+ sendmsg(<*type*>,<*op*>) A message identified by its *type* and *operation*.
+ sendmsg(<*type*>,<*op*>,<*stream*>) A message identified by its *type* and *operation*
+ with a stream *id*.
+ ==================================== ====================================================
+
+*Type* may be specified using message *name* or message *id*.
+
+*Op* may be specified using operation *name* or operation *id*.
+
+Stream *id* is an integer in the range 0..3.
+
+Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
+or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+
+Each message type supports specific operations:
+
+ ====================== ========== ============================== ============ ==========
+ Message name Message Id Supported Operations Operation Id Stream Id
+ ====================== ========== ============================== ============ ==========
+ MSG_INTERRUPT 1 \- \- \-
+ MSG_GS 2 GS_OP_CUT 1 Optional
+ \ GS_OP_EMIT 2 Optional
+ \ GS_OP_EMIT_CUT 3 Optional
+ MSG_GS_DONE 3 GS_OP_NOP 0 \-
+ \ GS_OP_CUT 1 Optional
+ \ GS_OP_EMIT 2 Optional
+ \ GS_OP_EMIT_CUT 3 Optional
+ MSG_SAVEWAVE 4 \- \- \-
+ MSG_STALL_WAVE_GEN 5 \- \- \-
+ MSG_HALT_WAVES 6 \- \- \-
+ MSG_ORDERED_PS_DONE 7 \- \- \-
+ MSG_GS_ALLOC_REQ 9 \- \- \-
+ MSG_GET_DOORBELL 10 \- \- \-
+ MSG_GET_DDID 11 \- \- \-
+ MSG_SYSMSG 15 SYSMSG_OP_ECC_ERR_INTERRUPT 1 \-
+ \ SYSMSG_OP_REG_RD 2 \-
+ \ SYSMSG_OP_TTRACE_PC 4 \-
+ ====================== ========== ============================== ============ ==========
+
+*Sendmsg* arguments are validated depending on how *type* value is specified:
+
+* If message *type* is specified by name, arguments values must satisfy limitations detailed in the table above.
+* If message *type* is specified as a number, each argument must not exceed corresponding value range (see the first table).
+
+Examples:
+
+.. parsed-literal::
+
+ // numeric message code
+ msg = 0x10
+ s_sendmsg 0x12
+ s_sendmsg msg + 2
+
+ // sendmsg with strict arguments validation
+ s_sendmsg sendmsg(MSG_INTERRUPT)
+ s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT)
+ s_sendmsg sendmsg(MSG_GS, 2)
+ s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_EMIT_CUT, 1)
+ s_sendmsg sendmsg(MSG_SYSMSG, SYSMSG_OP_TTRACE_PC)
+ s_sendmsg sendmsg(MSG_GET_DOORBELL)
+
+ // sendmsg with validation of value range only
+ msg = 2
+ op = 3
+ stream = 1
+ s_sendmsg sendmsg(msg, op, stream)
+ s_sendmsg sendmsg(2, GS_OP_CUT)
diff --git a/llvm/docs/AMDGPU/gfx1030_opt.rst b/llvm/docs/AMDGPU/gfx1030_opt.rst
new file mode 100644
index 0000000000000..6921193602257
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_opt.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_opt:
+
+opt
+===
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
diff --git a/llvm/docs/AMDGPU/gfx1030_param.rst b/llvm/docs/AMDGPU/gfx1030_param.rst
new file mode 100644
index 0000000000000..7b333cd9b81fd
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_param.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_param:
+
+param
+=====
+
+Interpolation parameter to read:
+
+ ============ ===================================
+ Syntax Description
+ ============ ===================================
+ p0 Parameter *P0*.
+ p10 Parameter *P10*.
+ p20 Parameter *P20*.
+ ============ ===================================
diff --git a/llvm/docs/AMDGPU/gfx1030_saddr_9cd3cf.rst b/llvm/docs/AMDGPU/gfx1030_saddr_9cd3cf.rst
new file mode 100644
index 0000000000000..97901505e9bb3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_saddr_9cd3cf.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_saddr_9cd3cf:
+
+saddr
+=====
+
+A 64-bit flat global address.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx1030_saddr_beaa25.rst b/llvm/docs/AMDGPU/gfx1030_saddr_beaa25.rst
new file mode 100644
index 0000000000000..5860bdba1acf8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_saddr_beaa25.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_saddr_beaa25:
+
+saddr
+=====
+
+An optional 64-bit flat global address. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+See :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>` for description of available addressing modes.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx1030_saddr_d75725.rst b/llvm/docs/AMDGPU/gfx1030_saddr_d75725.rst
new file mode 100644
index 0000000000000..62aa21a85b949
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_saddr_d75725.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_saddr_d75725:
+
+saddr
+=====
+
+An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+* Offset = [:ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`] + [:ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>`] + :ref:`offset12s<amdgpu_synid_flat_offset12s>`.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx1030_sbase_010ce0.rst b/llvm/docs/AMDGPU/gfx1030_sbase_010ce0.rst
new file mode 100644
index 0000000000000..a26109ddf98f8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_sbase_010ce0.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_sbase_010ce0:
+
+sbase
+=====
+
+A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx1030_sbase_020892.rst b/llvm/docs/AMDGPU/gfx1030_sbase_020892.rst
new file mode 100644
index 0000000000000..44e64c78c2576
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_sbase_020892.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_sbase_020892:
+
+sbase
+=====
+
+A 64-bit base address for scalar memory operations.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx1030_sdst_0804b1.rst b/llvm/docs/AMDGPU/gfx1030_sdst_0804b1.rst
new file mode 100644
index 0000000000000..02a65f65ad029
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_sdst_0804b1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_sdst_0804b1:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx1030_sdst_2e4c2a.rst b/llvm/docs/AMDGPU/gfx1030_sdst_2e4c2a.rst
new file mode 100644
index 0000000000000..a1b94f4c9d706
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_sdst_2e4c2a.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_sdst_2e4c2a:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx1030_sdst_362c37.rst b/llvm/docs/AMDGPU/gfx1030_sdst_362c37.rst
new file mode 100644
index 0000000000000..c6d1d1ded3e83
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_sdst_362c37.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_sdst_362c37:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx1030_sdst_3759f6.rst b/llvm/docs/AMDGPU/gfx1030_sdst_3759f6.rst
new file mode 100644
index 0000000000000..383bce7b26b17
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_sdst_3759f6.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_sdst_3759f6:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 1 dword if wavefront size is 32, otherwise 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx1030_sdst_386c33.rst b/llvm/docs/AMDGPU/gfx1030_sdst_386c33.rst
new file mode 100644
index 0000000000000..5c438569c36e3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_sdst_386c33.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_sdst_386c33:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx1030_sdst_3bc700.rst b/llvm/docs/AMDGPU/gfx1030_sdst_3bc700.rst
new file mode 100644
index 0000000000000..5ee85ca9c705d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_sdst_3bc700.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_sdst_3bc700:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx1030_sdst_54e16e.rst b/llvm/docs/AMDGPU/gfx1030_sdst_54e16e.rst
new file mode 100644
index 0000000000000..fe11c50b5a30a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_sdst_54e16e.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_sdst_54e16e:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx1030_sdst_8078f5.rst b/llvm/docs/AMDGPU/gfx1030_sdst_8078f5.rst
new file mode 100644
index 0000000000000..643ab4e29c3ff
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_sdst_8078f5.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_sdst_8078f5:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx1030_sdst_ea3f10.rst b/llvm/docs/AMDGPU/gfx1030_sdst_ea3f10.rst
new file mode 100644
index 0000000000000..db47ef5a60af7
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_sdst_ea3f10.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_sdst_ea3f10:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx1030_simm32_6f0844.rst b/llvm/docs/AMDGPU/gfx1030_simm32_6f0844.rst
new file mode 100644
index 0000000000000..72a45484ca4f8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_simm32_6f0844.rst
@@ -0,0 +1,14 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_simm32_6f0844:
+
+simm32
+======
+
+A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
+The value is converted to *f32* as described :ref:`here<amdgpu_synid_conv>`.
diff --git a/llvm/docs/AMDGPU/gfx1030_simm32_a3e80c.rst b/llvm/docs/AMDGPU/gfx1030_simm32_a3e80c.rst
new file mode 100644
index 0000000000000..ee9b95cb43b50
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_simm32_a3e80c.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_simm32_a3e80c:
+
+simm32
+======
+
+An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value is truncated to 32 bits.
diff --git a/llvm/docs/AMDGPU/gfx1030_simm32_be0c1c.rst b/llvm/docs/AMDGPU/gfx1030_simm32_be0c1c.rst
new file mode 100644
index 0000000000000..c35a008db9a7d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_simm32_be0c1c.rst
@@ -0,0 +1,14 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_simm32_be0c1c:
+
+simm32
+======
+
+A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
+The value is converted to *f16* as described :ref:`here<amdgpu_synid_conv>`.
diff --git a/llvm/docs/AMDGPU/gfx1030_soffset_59fade.rst b/llvm/docs/AMDGPU/gfx1030_soffset_59fade.rst
new file mode 100644
index 0000000000000..d3e72ae1a635c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_soffset_59fade.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_soffset_59fade:
+
+soffset
+=======
+
+An unsigned 20-bit offset added to the base address to get memory address.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm20<amdgpu_synid_uimm20>`
diff --git a/llvm/docs/AMDGPU/gfx1030_soffset_c40a5a.rst b/llvm/docs/AMDGPU/gfx1030_soffset_c40a5a.rst
new file mode 100644
index 0000000000000..6f82eef187f39
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_soffset_c40a5a.rst
@@ -0,0 +1,20 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_soffset_c40a5a:
+
+soffset
+=======
+
+An offset added to the base address to get memory address.
+
+* If offset is specified as a register, it supplies an unsigned byte offset.
+* If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`simm21<amdgpu_synid_simm21>`
diff --git a/llvm/docs/AMDGPU/gfx1030_soffset_fef808.rst b/llvm/docs/AMDGPU/gfx1030_soffset_fef808.rst
new file mode 100644
index 0000000000000..9bbde28d1bcd3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_soffset_fef808.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_soffset_fef808:
+
+soffset
+=======
+
+An unsigned byte offset.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx1030_src_37d670.rst b/llvm/docs/AMDGPU/gfx1030_src_37d670.rst
new file mode 100644
index 0000000000000..ff2469c4222dc
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_src_37d670.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_src_37d670:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx1030_src_516946.rst b/llvm/docs/AMDGPU/gfx1030_src_516946.rst
new file mode 100644
index 0000000000000..e1696e41ed4e0
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_src_516946.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_src_516946:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`
diff --git a/llvm/docs/AMDGPU/gfx1030_src_823582.rst b/llvm/docs/AMDGPU/gfx1030_src_823582.rst
new file mode 100644
index 0000000000000..004824fafb588
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_src_823582.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_src_823582:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx1030_src_c27036.rst b/llvm/docs/AMDGPU/gfx1030_src_c27036.rst
new file mode 100644
index 0000000000000..ba395e7f8a970
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_src_c27036.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_src_c27036:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`ival<amdgpu_synid_ival>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx1030_src_cf1cda.rst b/llvm/docs/AMDGPU/gfx1030_src_cf1cda.rst
new file mode 100644
index 0000000000000..0fe49944c2949
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_src_cf1cda.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_src_cf1cda:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx1030_src_d5cd94.rst b/llvm/docs/AMDGPU/gfx1030_src_d5cd94.rst
new file mode 100644
index 0000000000000..6e4fd226f9f15
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_src_d5cd94.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_src_d5cd94:
+
+src
+===
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx1030_src_e0345d.rst b/llvm/docs/AMDGPU/gfx1030_src_e0345d.rst
new file mode 100644
index 0000000000000..7ffbc80a700ff
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_src_e0345d.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_src_e0345d:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`ival<amdgpu_synid_ival>`
diff --git a/llvm/docs/AMDGPU/gfx1030_src_e9e6db.rst b/llvm/docs/AMDGPU/gfx1030_src_e9e6db.rst
new file mode 100644
index 0000000000000..bc0ad8b2bfe5f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_src_e9e6db.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_src_e9e6db:
+
+src
+===
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`ival<amdgpu_synid_ival>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx1030_srsrc_5dafbc.rst b/llvm/docs/AMDGPU/gfx1030_srsrc_5dafbc.rst
new file mode 100644
index 0000000000000..cdd3298b89044
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_srsrc_5dafbc.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_srsrc_5dafbc:
+
+srsrc
+=====
+
+Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx1030_srsrc_cf7132.rst b/llvm/docs/AMDGPU/gfx1030_srsrc_cf7132.rst
new file mode 100644
index 0000000000000..7dee21e0bf792
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_srsrc_cf7132.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_srsrc_cf7132:
+
+srsrc
+=====
+
+Image resource constant which defines the location of the image buffer in memory, its dimensions, tiling, and data format.
+
+*Size:* 8 dwords by default, 4 dwords if :ref:`r128<amdgpu_synid_r128>` is specified.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx1030_srsrc_e73d16.rst b/llvm/docs/AMDGPU/gfx1030_srsrc_e73d16.rst
new file mode 100644
index 0000000000000..2a31e94d37f7d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_srsrc_e73d16.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_srsrc_e73d16:
+
+srsrc
+=====
+
+Buffer resource constant which defines the address and characteristics of the buffer in memory.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx1030_ssamp.rst b/llvm/docs/AMDGPU/gfx1030_ssamp.rst
new file mode 100644
index 0000000000000..da38b98b16261
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_ssamp.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_ssamp:
+
+ssamp
+=====
+
+Sampler constant used to specify filtering options applied to the image data after it is read.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx1030_ssrc_054e2a.rst b/llvm/docs/AMDGPU/gfx1030_ssrc_054e2a.rst
new file mode 100644
index 0000000000000..140ff47568651
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_ssrc_054e2a.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_ssrc_054e2a:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx1030_ssrc_2a042f.rst b/llvm/docs/AMDGPU/gfx1030_ssrc_2a042f.rst
new file mode 100644
index 0000000000000..7dbc629a83351
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_ssrc_2a042f.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_ssrc_2a042f:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx1030_ssrc_3ec588.rst b/llvm/docs/AMDGPU/gfx1030_ssrc_3ec588.rst
new file mode 100644
index 0000000000000..d127506b90102
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_ssrc_3ec588.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_ssrc_3ec588:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 1 dword if wavefront size is 32, otherwise 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
diff --git a/llvm/docs/AMDGPU/gfx1030_ssrc_460c63.rst b/llvm/docs/AMDGPU/gfx1030_ssrc_460c63.rst
new file mode 100644
index 0000000000000..759d813054fd1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_ssrc_460c63.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_ssrc_460c63:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx1030_ssrc_48e8e7.rst b/llvm/docs/AMDGPU/gfx1030_ssrc_48e8e7.rst
new file mode 100644
index 0000000000000..9469ebf800cfb
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_ssrc_48e8e7.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_ssrc_48e8e7:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx1030_ssrc_6fbc49.rst b/llvm/docs/AMDGPU/gfx1030_ssrc_6fbc49.rst
new file mode 100644
index 0000000000000..63b802fefcf90
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_ssrc_6fbc49.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_ssrc_6fbc49:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx1030_ssrc_7da351.rst b/llvm/docs/AMDGPU/gfx1030_ssrc_7da351.rst
new file mode 100644
index 0000000000000..0a6cdf9153042
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_ssrc_7da351.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_ssrc_7da351:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx1030_ssrc_81ba27.rst b/llvm/docs/AMDGPU/gfx1030_ssrc_81ba27.rst
new file mode 100644
index 0000000000000..4b514201501fc
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_ssrc_81ba27.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_ssrc_81ba27:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx1030_ssrc_9a4448.rst b/llvm/docs/AMDGPU/gfx1030_ssrc_9a4448.rst
new file mode 100644
index 0000000000000..70187571912f9
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_ssrc_9a4448.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_ssrc_9a4448:
+
+ssrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx1030_tgt.rst b/llvm/docs/AMDGPU/gfx1030_tgt.rst
new file mode 100644
index 0000000000000..7f14a7b01c3a9
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_tgt.rst
@@ -0,0 +1,24 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_tgt:
+
+tgt
+===
+
+An export target:
+
+ ================== ===================================
+ Syntax Description
+ ================== ===================================
+ pos{0..4} Copy vertex position 0..4.
+ param{0..31} Copy vertex parameter 0..31.
+ mrt{0..7} Copy pixel color to the MRTs 0..7.
+ mrtz Copy pixel depth (Z) data.
+ prim Copy primitive (connectivity) data.
+ null Copy nothing.
+ ================== ===================================
diff --git a/llvm/docs/AMDGPU/gfx1030_type_deviation.rst b/llvm/docs/AMDGPU/gfx1030_type_deviation.rst
new file mode 100644
index 0000000000000..0e66137e63fbe
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_type_deviation.rst
@@ -0,0 +1,13 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_type_deviation:
+
+Type Deviation
+==============
+
+*Type* of this operand
diff ers from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_mnemo>`. This tag specifies actual operand *type*.
diff --git a/llvm/docs/AMDGPU/gfx1030_vaddr_373b95.rst b/llvm/docs/AMDGPU/gfx1030_vaddr_373b95.rst
new file mode 100644
index 0000000000000..b5e78bbc32acb
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vaddr_373b95.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vaddr_373b95:
+
+vaddr
+=====
+
+An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+* Offset = [:ref:`vaddr<amdgpu_synid_gfx1030_vaddr_373b95>`] + [:ref:`saddr<amdgpu_synid_gfx1030_saddr_d75725>`] + :ref:`offset12s<amdgpu_synid_flat_offset12s>`.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vaddr_49d53a.rst b/llvm/docs/AMDGPU/gfx1030_vaddr_49d53a.rst
new file mode 100644
index 0000000000000..dcf198c8a6434
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vaddr_49d53a.rst
@@ -0,0 +1,29 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vaddr_49d53a:
+
+vaddr
+=====
+
+Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
+
+This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`.
+
+*Size:* 8-12 dwords. Actual size depends on :ref:`a16<amdgpu_synid_a16>`.
+
+* If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 8-12 dwords.
+* If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 8 dwords. Opcodes which require more than 8 dwords for address size must specify 16 dwords due to a limited range of supported register sequences.
+
+ Examples:
+
+ .. parsed-literal::
+
+ image_bvh_intersect_ray v[4:7], v[9:24], s[4:7]
+ image_bvh_intersect_ray v[39:42], [v5, v4, v2, v1, v7, v3, v0, v6], s[12:15] a16
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vaddr_9aeece.rst b/llvm/docs/AMDGPU/gfx1030_vaddr_9aeece.rst
new file mode 100644
index 0000000000000..da181af6c5820
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vaddr_9aeece.rst
@@ -0,0 +1,20 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vaddr_9aeece:
+
+vaddr
+=====
+
+A 64-bit flat global address or a 32-bit offset depending on addressing mode:
+
+* Address = :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>` + :ref:`offset12s<amdgpu_synid_flat_offset12s>`. :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` set to :ref:`off<amdgpu_synid_off>`.
+* Address = :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` + :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>` + :ref:`offset12s<amdgpu_synid_flat_offset12s>`. :ref:`vaddr<amdgpu_synid_gfx1030_vaddr_9aeece>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid_gfx1030_saddr_beaa25>` is not :ref:`off<amdgpu_synid_off>`.
+
+*Size:* 1 or 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vaddr_9f7133.rst b/llvm/docs/AMDGPU/gfx1030_vaddr_9f7133.rst
new file mode 100644
index 0000000000000..77d68860e0b9c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vaddr_9f7133.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vaddr_9f7133:
+
+vaddr
+=====
+
+A 64-bit flat address.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vaddr_b73dc0.rst b/llvm/docs/AMDGPU/gfx1030_vaddr_b73dc0.rst
new file mode 100644
index 0000000000000..f16e99df01fab
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vaddr_b73dc0.rst
@@ -0,0 +1,22 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vaddr_b73dc0:
+
+vaddr
+=====
+
+This is an optional operand which may specify offset and/or index.
+
+*Size:* 0, 1 or 2 dwords. Size is controlled by modifiers :ref:`offen<amdgpu_synid_offen>` and :ref:`idxen<amdgpu_synid_idxen>`:
+
+* If only :ref:`idxen<amdgpu_synid_idxen>` is specified, this operand supplies an index. Size is 1 dword.
+* If only :ref:`offen<amdgpu_synid_offen>` is specified, this operand supplies an offset. Size is 1 dword.
+* If both modifiers are specified, index is in the first register and offset is in the second. Size is 2 dwords.
+* If none of these modifiers are specified, this operand must be set to :ref:`off<amdgpu_synid_off>`.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vaddr_cdc744.rst b/llvm/docs/AMDGPU/gfx1030_vaddr_cdc744.rst
new file mode 100644
index 0000000000000..4f365b2f2023f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vaddr_cdc744.rst
@@ -0,0 +1,22 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vaddr_cdc744:
+
+vaddr
+=====
+
+Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
+
+This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`.
+
+*Size:* 1-13 dwords. Actual size depends on syntax, opcode, :ref:`dim<amdgpu_synid_dim>` and :ref:`a16<amdgpu_synid_a16>`.
+
+* If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
+* If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 1-8 dwords. Opcodes which require more than 8 dwords for address size must specify 16 dwords due to a limited range of supported register sequences.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vaddr_f20ee4.rst b/llvm/docs/AMDGPU/gfx1030_vaddr_f20ee4.rst
new file mode 100644
index 0000000000000..66d03e2fdc819
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vaddr_f20ee4.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vaddr_f20ee4:
+
+vaddr
+=====
+
+An offset from the start of GDS/LDS memory.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vcc.rst b/llvm/docs/AMDGPU/gfx1030_vcc.rst
new file mode 100644
index 0000000000000..5313d1228419d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vcc.rst
@@ -0,0 +1,16 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vcc:
+
+vcc
+===
+
+Vector condition code. This operand depends on wavefront size:
+
+* Should be :ref:`vcc_lo<amdgpu_synid_vcc_lo>` if wavefront size is 32.
+* Should be :ref:`vcc<amdgpu_synid_vcc>` if wavefront size is 64.
diff --git a/llvm/docs/AMDGPU/gfx1030_vdata0_6802ce.rst b/llvm/docs/AMDGPU/gfx1030_vdata0_6802ce.rst
new file mode 100644
index 0000000000000..3be757d0a7b8a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdata0_6802ce.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdata0_6802ce:
+
+vdata0
+======
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdata0_fd235e.rst b/llvm/docs/AMDGPU/gfx1030_vdata0_fd235e.rst
new file mode 100644
index 0000000000000..30da0022e20ae
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdata0_fd235e.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdata0_fd235e:
+
+vdata0
+======
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdata1_6802ce.rst b/llvm/docs/AMDGPU/gfx1030_vdata1_6802ce.rst
new file mode 100644
index 0000000000000..1fc0102efb1ff
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdata1_6802ce.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdata1_6802ce:
+
+vdata1
+======
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdata1_fd235e.rst b/llvm/docs/AMDGPU/gfx1030_vdata1_fd235e.rst
new file mode 100644
index 0000000000000..8851f9de42643
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdata1_fd235e.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdata1_fd235e:
+
+vdata1
+======
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdata_15d255.rst b/llvm/docs/AMDGPU/gfx1030_vdata_15d255.rst
new file mode 100644
index 0000000000000..9be0ef2677064
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdata_15d255.rst
@@ -0,0 +1,20 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdata_15d255:
+
+vdata
+=====
+
+Image data to store by an *image_store* instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`d16<amdgpu_synid_d16>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+* :ref:`d16<amdgpu_synid_d16>` specifies that data in registers are packed; each value occupies 16 bits.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdata_325b78.rst b/llvm/docs/AMDGPU/gfx1030_vdata_325b78.rst
new file mode 100644
index 0000000000000..c2d8547f86812
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdata_325b78.rst
@@ -0,0 +1,26 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdata_325b78:
+
+vdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+ Note: the surface data format is indicated in the image resource constant but not in the instruction.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdata_4d8ecf.rst b/llvm/docs/AMDGPU/gfx1030_vdata_4d8ecf.rst
new file mode 100644
index 0000000000000..8912c22c9599a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdata_4d8ecf.rst
@@ -0,0 +1,26 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdata_4d8ecf:
+
+vdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+ Note: the surface data format is indicated in the image resource constant but not in the instruction.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdata_56f215.rst b/llvm/docs/AMDGPU/gfx1030_vdata_56f215.rst
new file mode 100644
index 0000000000000..5981d50ef8a2e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdata_56f215.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdata_56f215:
+
+vdata
+=====
+
+Instruction input.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdata_6802ce.rst b/llvm/docs/AMDGPU/gfx1030_vdata_6802ce.rst
new file mode 100644
index 0000000000000..46b7a4415da3b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdata_6802ce.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdata_6802ce:
+
+vdata
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdata_87fb90.rst b/llvm/docs/AMDGPU/gfx1030_vdata_87fb90.rst
new file mode 100644
index 0000000000000..8bccc79db430d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdata_87fb90.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdata_87fb90:
+
+vdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdata_b2a787.rst b/llvm/docs/AMDGPU/gfx1030_vdata_b2a787.rst
new file mode 100644
index 0000000000000..c4ea1ef2af03e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdata_b2a787.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdata_b2a787:
+
+vdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdata_c08393.rst b/llvm/docs/AMDGPU/gfx1030_vdata_c08393.rst
new file mode 100644
index 0000000000000..ea35a696d6b39
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdata_c08393.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdata_c08393:
+
+vdata
+=====
+
+Image data to store by an *image_store* instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` which may specify from 1 to 4 data elements. Each data element occupies 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdata_c61803.rst b/llvm/docs/AMDGPU/gfx1030_vdata_c61803.rst
new file mode 100644
index 0000000000000..c852642a6f082
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdata_c61803.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdata_c61803:
+
+vdata
+=====
+
+Input data for an atomic instruction.
+
+Optionally may serve as an output data:
+
+* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdata_e016a1.rst b/llvm/docs/AMDGPU/gfx1030_vdata_e016a1.rst
new file mode 100644
index 0000000000000..fe9ab98b8db5a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdata_e016a1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdata_e016a1:
+
+vdata
+=====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdata_fd235e.rst b/llvm/docs/AMDGPU/gfx1030_vdata_fd235e.rst
new file mode 100644
index 0000000000000..d48ceb15daaa6
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdata_fd235e.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdata_fd235e:
+
+vdata
+=====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdst_3d7dcf.rst b/llvm/docs/AMDGPU/gfx1030_vdst_3d7dcf.rst
new file mode 100644
index 0000000000000..bebaa7b3a1449
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdst_3d7dcf.rst
@@ -0,0 +1,20 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdst_3d7dcf:
+
+vdst
+====
+
+Image data to load by an image instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies 1 dword.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdst_463513.rst b/llvm/docs/AMDGPU/gfx1030_vdst_463513.rst
new file mode 100644
index 0000000000000..ecbea5a836110
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdst_463513.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdst_463513:
+
+vdst
+====
+
+Data returned by a 64-bit atomic flat instruction.
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdst_473a69.rst b/llvm/docs/AMDGPU/gfx1030_vdst_473a69.rst
new file mode 100644
index 0000000000000..d30b6427a1e61
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdst_473a69.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdst_473a69:
+
+vdst
+====
+
+Image data to load by an image instruction.
+
+*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`, :ref:`tfe<amdgpu_synid_tfe>` and :ref:`d16<amdgpu_synid_d16>`:
+
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+* :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
+* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdst_48d3a8.rst b/llvm/docs/AMDGPU/gfx1030_vdst_48d3a8.rst
new file mode 100644
index 0000000000000..caf83564d7eca
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdst_48d3a8.rst
@@ -0,0 +1,22 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdst_48d3a8:
+
+vdst
+====
+
+Image data to load by an *image_gather4* instruction.
+
+*Size:* 4 data elements by default. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+
+:ref:`d16<amdgpu_synid_d16>` and :ref:`tfe<amdgpu_synid_tfe>` affect operand size as follows:
+
+* :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
+* :ref:`tfe<amdgpu_synid_tfe>` adds one dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdst_48e42f.rst b/llvm/docs/AMDGPU/gfx1030_vdst_48e42f.rst
new file mode 100644
index 0000000000000..5601aff17ad6d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdst_48e42f.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdst_48e42f:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdst_5d50a1.rst b/llvm/docs/AMDGPU/gfx1030_vdst_5d50a1.rst
new file mode 100644
index 0000000000000..7b789abd5616b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdst_5d50a1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdst_5d50a1:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdst_69a144.rst b/llvm/docs/AMDGPU/gfx1030_vdst_69a144.rst
new file mode 100644
index 0000000000000..7f383c604a847
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdst_69a144.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdst_69a144:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdst_719833.rst b/llvm/docs/AMDGPU/gfx1030_vdst_719833.rst
new file mode 100644
index 0000000000000..8a53b669b8cb5
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdst_719833.rst
@@ -0,0 +1,21 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdst_719833:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+If :ref:`lds<amdgpu_synid_lds>` is specified, this operand is ignored by H/W and data are stored directly into LDS.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+ Note that :ref:`tfe<amdgpu_synid_tfe>` and :ref:`lds<amdgpu_synid_lds>` cannot be used together.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdst_89680f.rst b/llvm/docs/AMDGPU/gfx1030_vdst_89680f.rst
new file mode 100644
index 0000000000000..322c0d8782738
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdst_89680f.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdst_89680f:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdst_a49b76.rst b/llvm/docs/AMDGPU/gfx1030_vdst_a49b76.rst
new file mode 100644
index 0000000000000..4b7d8c31ee4ed
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdst_a49b76.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdst_a49b76:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 3 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdst_bdb32f.rst b/llvm/docs/AMDGPU/gfx1030_vdst_bdb32f.rst
new file mode 100644
index 0000000000000..ae7aab6e88fc9
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdst_bdb32f.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdst_bdb32f:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdst_d0dc43.rst b/llvm/docs/AMDGPU/gfx1030_vdst_d0dc43.rst
new file mode 100644
index 0000000000000..435e8f91a33c8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdst_d0dc43.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdst_d0dc43:
+
+vdst
+====
+
+Data returned by a 32-bit atomic flat instruction.
+
+This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdst_d7c57e.rst b/llvm/docs/AMDGPU/gfx1030_vdst_d7c57e.rst
new file mode 100644
index 0000000000000..40c17e7b089e0
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdst_d7c57e.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdst_d7c57e:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdst_f47754.rst b/llvm/docs/AMDGPU/gfx1030_vdst_f47754.rst
new file mode 100644
index 0000000000000..9fd585726cf4e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdst_f47754.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdst_f47754:
+
+vdst
+====
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vdst_f8490d.rst b/llvm/docs/AMDGPU/gfx1030_vdst_f8490d.rst
new file mode 100644
index 0000000000000..89b252a91516b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vdst_f8490d.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vdst_f8490d:
+
+vdst
+====
+
+Image data to load by an image instruction.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vsrc_533a4e.rst b/llvm/docs/AMDGPU/gfx1030_vsrc_533a4e.rst
new file mode 100644
index 0000000000000..c948a55b1ab15
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vsrc_533a4e.rst
@@ -0,0 +1,28 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vsrc_533a4e:
+
+vsrc
+====
+
+Data to copy to export buffers. This is an optional operand. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
+
+:ref:`compr<amdgpu_synid_compr>` modifier indicates use of compressed (16-bit) data. This limits number of source operands from 4 to 2:
+
+* src0 and src1 must specify the first register (or :ref:`off<amdgpu_synid_off>`).
+* src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
+
+An example:
+
+.. parsed-literal::
+
+ exp mrtz v3, v3, off, off compr
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vsrc_6802ce.rst b/llvm/docs/AMDGPU/gfx1030_vsrc_6802ce.rst
new file mode 100644
index 0000000000000..5cbb0357cec8d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vsrc_6802ce.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vsrc_6802ce:
+
+vsrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vsrc_e016a1.rst b/llvm/docs/AMDGPU/gfx1030_vsrc_e016a1.rst
new file mode 100644
index 0000000000000..212b769325b4e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vsrc_e016a1.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vsrc_e016a1:
+
+vsrc
+====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_vsrc_fd235e.rst b/llvm/docs/AMDGPU/gfx1030_vsrc_fd235e.rst
new file mode 100644
index 0000000000000..700f32b9a4f2e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_vsrc_fd235e.rst
@@ -0,0 +1,17 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_vsrc_fd235e:
+
+vsrc
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1030_waitcnt.rst b/llvm/docs/AMDGPU/gfx1030_waitcnt.rst
new file mode 100644
index 0000000000000..e88230b7d361b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1030_waitcnt.rst
@@ -0,0 +1,64 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1030_waitcnt:
+
+waitcnt
+=======
+
+Counts of outstanding instructions to wait for.
+
+The bits of this operand have the following meaning:
+
+ ========== ========= ================================================ ============
+ High Bits Low Bits Description Value Range
+ ========== ========= ================================================ ============
+ 15:14 3:0 VM_CNT: vector memory operations count. 0..63
+ \- 6:4 EXP_CNT: export count. 0..7
+ \- 13:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..63
+ ========== ========= ================================================ ============
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
+* A combination of *vmcnt*, *expcnt*, *lgkmcnt* and other values described below.
+
+ ====================== ======================================================================
+ Syntax Description
+ ====================== ======================================================================
+ vmcnt(<*N*>) A VM_CNT value. *N* must not exceed the largest VM_CNT value.
+ expcnt(<*N*>) An EXP_CNT value. *N* must not exceed the largest EXP_CNT value.
+ lgkmcnt(<*N*>) An LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value.
+ vmcnt_sat(<*N*>) A VM_CNT value computed as min(*N*, the largest VM_CNT value).
+ expcnt_sat(<*N*>) An EXP_CNT value computed as min(*N*, the largest EXP_CNT value).
+ lgkmcnt_sat(<*N*>) An LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value).
+ ====================== ======================================================================
+
+These values may be specified in any order. Spaces, ampersands and commas may be used as optional separators.
+
+*N* is either an
+:ref:`integer number<amdgpu_synid_integer_number>` or an
+:ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+
+Examples:
+
+.. parsed-literal::
+
+ vm_cnt = 1
+ exp_cnt = 2
+ lgkm_cnt = 3
+ cnt = vm_cnt | (exp_cnt << 4) | (lgkm_cnt << 8)
+
+ s_waitcnt cnt
+ s_waitcnt 1 | (2 << 4) | (3 << 8) // the same as above
+ s_waitcnt vmcnt(1) expcnt(2) lgkmcnt(3) // the same as above
+ s_waitcnt vmcnt(vm_cnt) expcnt(exp_cnt) lgkmcnt(lgkm_cnt) // the same as above
+
+ s_waitcnt vmcnt(1)
+ s_waitcnt expcnt(2) lgkmcnt(3)
+ s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3)
+ s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2)
diff --git a/llvm/docs/AMDGPUInstructionSyntax.rst b/llvm/docs/AMDGPUInstructionSyntax.rst
index e3fabe0df1e9f..b4c984745b649 100644
--- a/llvm/docs/AMDGPUInstructionSyntax.rst
+++ b/llvm/docs/AMDGPUInstructionSyntax.rst
@@ -167,12 +167,7 @@ Syntax
Syntax of generic operands is described :doc:`in this document<AMDGPUOperandSyntax>`.
-For detailed information about operands follow *operand links* in GPU-specific documents:
-
-* :doc:`GFX7<AMDGPU/AMDGPUAsmGFX7>`
-* :doc:`GFX8<AMDGPU/AMDGPUAsmGFX8>`
-* :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>`
-* :doc:`GFX10<AMDGPU/AMDGPUAsmGFX10>`
+For detailed information about operands follow *operand links* in GPU-specific documents.
Modifiers
=========
@@ -182,10 +177,4 @@ Syntax
Syntax of modifiers is described :doc:`in this document<AMDGPUModifierSyntax>`.
-Information about modifiers supported for individual instructions may be found in GPU-specific documents:
-
-* :doc:`GFX7<AMDGPU/AMDGPUAsmGFX7>`
-* :doc:`GFX8<AMDGPU/AMDGPUAsmGFX8>`
-* :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>`
-* :doc:`GFX10<AMDGPU/AMDGPUAsmGFX10>`
-
+Information about modifiers supported for individual instructions may be found in GPU-specific documents.
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index ddaf819139962..bd6cdd84e3a50 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -18,6 +18,7 @@ User Guide for AMDGPU Backend
AMDGPU/AMDGPUAsmGFX90a
AMDGPU/AMDGPUAsmGFX10
AMDGPU/AMDGPUAsmGFX1011
+ AMDGPU/AMDGPUAsmGFX1030
AMDGPUModifierSyntax
AMDGPUOperandSyntax
AMDGPUInstructionSyntax
@@ -14180,29 +14181,43 @@ Links to detailed instruction syntax description may be found in the following
table. Note that features under development are not included
in this description.
- =================================== =======================================
- Core ISA ISA Extensions
- =================================== =======================================
- :doc:`GFX7<AMDGPU/AMDGPUAsmGFX7>` \-
- :doc:`GFX8<AMDGPU/AMDGPUAsmGFX8>` \-
- :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>` :doc:`gfx900<AMDGPU/AMDGPUAsmGFX900>`
+ ============= ============================================= =======================================
+ Architecture Core ISA ISA Variants and Extensions
+ ============= ============================================= =======================================
+ GCN 2 :doc:`GFX7<AMDGPU/AMDGPUAsmGFX7>` \-
+ GCN 3, GCN 4 :doc:`GFX8<AMDGPU/AMDGPUAsmGFX8>` \-
+ GCN 5 :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>` :doc:`gfx900<AMDGPU/AMDGPUAsmGFX900>`
- :doc:`gfx902<AMDGPU/AMDGPUAsmGFX900>`
+ :doc:`gfx902<AMDGPU/AMDGPUAsmGFX900>`
- :doc:`gfx904<AMDGPU/AMDGPUAsmGFX904>`
+ :doc:`gfx904<AMDGPU/AMDGPUAsmGFX904>`
- :doc:`gfx906<AMDGPU/AMDGPUAsmGFX906>`
+ :doc:`gfx906<AMDGPU/AMDGPUAsmGFX906>`
- :doc:`gfx908<AMDGPU/AMDGPUAsmGFX908>`
+ :doc:`gfx909<AMDGPU/AMDGPUAsmGFX900>`
- :doc:`gfx909<AMDGPU/AMDGPUAsmGFX900>`
+ CDNA 1 :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>` :doc:`gfx908<AMDGPU/AMDGPUAsmGFX908>`
+ CDNA 2 :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>` :doc:`gfx90a<AMDGPU/AMDGPUAsmGFX90a>`
+ RDNA 1 :doc:`GFX10 RDNA1<AMDGPU/AMDGPUAsmGFX10>` :doc:`gfx1010<AMDGPU/AMDGPUAsmGFX10>`
- :doc:`gfx90a<AMDGPU/AMDGPUAsmGFX90a>`
+ :doc:`gfx1011<AMDGPU/AMDGPUAsmGFX1011>`
- :doc:`GFX10<AMDGPU/AMDGPUAsmGFX10>` :doc:`gfx1011<AMDGPU/AMDGPUAsmGFX1011>`
+ :doc:`gfx1012<AMDGPU/AMDGPUAsmGFX1011>`
- :doc:`gfx1012<AMDGPU/AMDGPUAsmGFX1011>`
- =================================== =======================================
+ RDNA 2 :doc:`GFX10 RDNA2<AMDGPU/AMDGPUAsmGFX1030>` :doc:`gfx1030<AMDGPU/AMDGPUAsmGFX1030>`
+
+ :doc:`gfx1031<AMDGPU/AMDGPUAsmGFX1030>`
+
+ :doc:`gfx1032<AMDGPU/AMDGPUAsmGFX1030>`
+
+ :doc:`gfx1033<AMDGPU/AMDGPUAsmGFX1030>`
+
+ :doc:`gfx1034<AMDGPU/AMDGPUAsmGFX1030>`
+
+ :doc:`gfx1035<AMDGPU/AMDGPUAsmGFX1030>`
+
+ :doc:`gfx1036<AMDGPU/AMDGPUAsmGFX1030>`
+ ============= ============================================= =======================================
For more information about instructions, their semantics and supported
combinations of operands, refer to one of instruction set architecture manuals
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