[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Wang Pengcheng via Phabricator via llvm-commits]

pcwang-thead updated this revision to Diff 418202.
pcwang-thead added a subscriber: lenary.
pcwang-thead added a comment.

- Support FastCC and disable GHC on RV32E.
- Don't use aligned registers to pass variadic arguments.
- Set stack alignment to 4-bytes for types with length of 2*XLEN.
- Add some tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70401/new/

https://reviews.llvm.org/D70401

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32e-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32e-abi.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVCallingConv.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
  llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
  llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32e.ll
  llvm/test/CodeGen/RISCV/rv32e.ll
  llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
  llvm/test/CodeGen/RISCV/stack-realignment.ll
  llvm/test/CodeGen/RISCV/target-abi-valid.ll
  llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
  llvm/test/CodeGen/RISCV/vararg.ll
  llvm/test/MC/RISCV/target-abi-invalid.s

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