[PATCH] D73643: [RISCV] Macro Fusion for RISC-V

[Zircon Liu via Phabricator via llvm-commits]

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Hi, I'd like to know if you are still interested in this work? There is a microarchitecture called XiangShan <https://github.com/OpenXiangShan/XiangShan> that actually supports instruction fusion.

We are working on support of this processor in LLVM, including macro fusion, and we hope to make our patches upstream. The fusion pairs are listed here <https://xiangshan-doc.readthedocs.io/zh_CN/latest/frontend/decode/> (translations needed)  and I suppose it's a good opportunity to introduce instruction fusion in the RISCV ecosystem of LLVM.


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