[PATCH] D122454: [RISCV] (and (not (srl X, C)), 1) to (sltiu (andi X, 2 << C), 1) when Zbs extension disable

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:384
 
+// Return an immediate value plus 32.
+def ImmPow2: SDNodeXForm<imm, [{
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This comment is duplicated from ImmPlus32.


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Comment at: llvm/test/CodeGen/RISCV/rv64zbs.ll:518
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    andi a0, a0, 256
+; RV64I-NEXT:    seqz a0, a0
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Shouldn't this be 128 not 256?


Repository:
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  https://reviews.llvm.org/D122454/new/

https://reviews.llvm.org/D122454