[PATCH] D122453: [test][AArch64] Add a test case for D121180 NFC

[Allen zhong via Phabricator via llvm-commits]

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Now, perform last active true vector combine only where
we're extracting from a flag-setting operation. But in
fact, the last active extracting will output LASTB + WHILELS,
and the WHILELS itself is a flag-setting operation, so
precommit this case to test the potentially further optimization.


https://reviews.llvm.org/D122453

Files:
  llvm/test/CodeGen/AArch64/sve-extract-element.ll


Index: llvm/test/CodeGen/AArch64/sve-extract-element.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-extract-element.ll
+++ llvm/test/CodeGen/AArch64/sve-extract-element.ll
@@ -501,6 +501,23 @@
   ret i1 %b
 }
 
+define i1 @test_last_8xi1(<vscale x 8 x i1> %a) #0 {
+; CHECK-LABEL: test_last_8xi1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cnth x8
+; CHECK-NEXT:    mov z0.h, p0/z, #1 // =0x1
+; CHECK-NEXT:    sub x8, x8, #1
+; CHECK-NEXT:    whilels p0.h, xzr, x8
+; CHECK-NEXT:    lastb w8, p0, z0.h
+; CHECK-NEXT:    and w0, w8, #0x1
+; CHECK-NEXT:    ret
+  %vscale = call i64 @llvm.vscale.i64()
+  %shl = shl nuw nsw i64 %vscale, 3
+  %idx = add nuw nsw i64 %shl, -1
+  %bit = extractelement <vscale x 8 x i1> %a, i64 %idx
+  ret i1 %bit
+}
+
 define i1 @test_lanex_4xi1(<vscale x 4 x i1> %a, i32 %x) #0 {
 ; CHECK-LABEL: test_lanex_4xi1:
 ; CHECK:       // %bb.0:
@@ -527,4 +544,6 @@
   ret i1 %b
 }
 
+declare i64 @llvm.vscale.i64()
+
 attributes #0 = { "target-features"="+sve" }


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