[PATCH] D121366: Allow ImproveChain to get past relaxed atomics

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:24066
+    if (const auto *AN = dyn_cast<AtomicSDNode>(N)) {
+      // PRE_INC / PRE_DEC allegedly not a relevant issue, can set this to zero
+      int64_t Offset = 0;
----------------
yoni-lavi wrote:
> craig.topper wrote:
> > I'm not sure what this comment is trying to say
> It's related to the case above (LSBaseSDNode) where `Offset` is computed to account for PRE_INC / PRE_DEC.
> 
> If I understood it right, this way of representing ptr increments as part of the memory access itself does not exist for the "atomic" SDNodes. Hence the `Offset = 0` and this comment.
> 
> 
The use "allegedly" and "issue" make it seem like there might be some like might be some problem or question here. Can you write it in a more confident way. Like "Atomic instructions don't have an offset"


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  https://reviews.llvm.org/D121366/new/

https://reviews.llvm.org/D121366