[PATCH] D122350: [WIP][X86SchedSandyBridge] update cost of COPY to 1 cycle from 0

[Nick Desaulniers via Phabricator via llvm-commits]

nickdesaulniers created this revision.
nickdesaulniers added reviewers: pengfei, craig.topper.
Herald added subscribers: StephenFan, javed.absar, hiraditya.
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nickdesaulniers requested review of this revision.
Herald added a project: LLVM.
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Not sure this is the approach we want to take; also doesn't update the
test regressions (for clarity to see what changed in
llvm/test/CodeGen/X86/scheduler-asm-moves.mir):

Failed Tests (12):

  LLVM :: CodeGen/X86/2009-03-23-MultiUseSched.ll
  LLVM :: CodeGen/X86/fp-load-trunc.ll
  LLVM :: CodeGen/X86/fp-trunc.ll
  LLVM :: CodeGen/X86/gather-addresses.ll
  LLVM :: CodeGen/X86/machine-combiner-int-vec.ll
  LLVM :: CodeGen/X86/machine-combiner-int.ll
  LLVM :: CodeGen/X86/recip-fastmath.ll
  LLVM :: CodeGen/X86/recip-fastmath2.ll
  LLVM :: CodeGen/X86/sqrt-fastmath-tune.ll
  LLVM :: CodeGen/X86/sqrt-fastmath.ll
  LLVM :: CodeGen/X86/vector-reduce-fadd-fast.ll
  LLVM :: CodeGen/X86/vector-reduce-fmul-fast.ll

Suggested by Craig Topper.

Fixes: https://github.com/llvm/llvm-project/issues/41914


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D122350

Files:
  llvm/lib/Target/X86/X86SchedSandyBridge.td
  llvm/test/CodeGen/X86/scheduler-asm-moves.mir


Index: llvm/test/CodeGen/X86/scheduler-asm-moves.mir
===================================================================
--- llvm/test/CodeGen/X86/scheduler-asm-moves.mir
+++ llvm/test/CodeGen/X86/scheduler-asm-moves.mir
@@ -123,6 +123,8 @@
     ; CHECK-LABEL: name: synproxy_send_tcp_ipv6
     ; CHECK: liveins: $eax, $edx
     ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edx
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32_abcd = COPY $eax
     ; CHECK-NEXT: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm $noreg, 1, $noreg, @csum_ipv6_magic_saddr, $noreg :: (dereferenceable load (s8) from `i8* getelementptr inbounds (%struct.in6_addr, %struct.in6_addr* @csum_ipv6_magic_saddr, i32 0, i32 0, i32 0)`)
     ; CHECK-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm $noreg, 1, $noreg, @csum_ipv6_magic_daddr, $noreg :: (dereferenceable load (s32) from @csum_ipv6_magic_daddr, !tbaa !4)
     ; CHECK-NEXT: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm $noreg, 1, $noreg, @csum_ipv6_magic_proto, $noreg :: (dereferenceable load (s32) from @csum_ipv6_magic_proto, !tbaa !4)
@@ -131,11 +133,9 @@
     ; CHECK-NEXT: MOV32mr $noreg, 1, $noreg, @csum_ipv6_magic_sum, $noreg, %2 :: (store (s32) into @csum_ipv6_magic_sum, !tbaa !4)
     ; CHECK-NEXT: [[MOV32rm2:%[0-9]+]]:gr32 = MOV32rm $noreg, 1, $noreg, @synproxy_send_tcp_ipv6_nskb, $noreg :: (dereferenceable load (s32) from `i8** bitcast (%struct.sk_buff** @synproxy_send_tcp_ipv6_nskb to i8**)`, !tbaa !9)
     ; CHECK-NEXT: OR8mi [[MOV32rm2]], 1, $noreg, 0, $noreg, 3, implicit-def dead $eflags :: (store (s8) into %ir.4), (load (s8) from %ir.4)
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32_abcd = COPY $eax
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $edx
-    ; CHECK-NEXT: [[MOV8rm1:%[0-9]+]]:gr8 = MOV8rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s8) from %ir.5, !tbaa !11)
+    ; CHECK-NEXT: [[MOV8rm1:%[0-9]+]]:gr8 = MOV8rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s8) from %ir.5, !tbaa !11)
     ; CHECK-NEXT: MOV8mr $noreg, 1, $noreg, @synproxy_send_tcp_ipv6_fl6, $noreg, [[MOV8rm1]] :: (store (s8) into `i8* getelementptr inbounds (%struct.in6_addr, %struct.in6_addr* @synproxy_send_tcp_ipv6_fl6, i32 0, i32 0, i32 0)`, !tbaa !11)
-    ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY]].sub_8bit
+    ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]].sub_8bit
     ; CHECK-NEXT: $eax = COPY [[MOVZX32rr8_]]
     ; CHECK-NEXT: TCRETURNdi @fl6nthsecurity_skb_classify_flow, 0, csr_32, implicit $esp, implicit $ssp, implicit $eax
     %1:gr32 = COPY $edx
Index: llvm/lib/Target/X86/X86SchedSandyBridge.td
===================================================================
--- llvm/lib/Target/X86/X86SchedSandyBridge.td
+++ llvm/lib/Target/X86/X86SchedSandyBridge.td
@@ -111,6 +111,7 @@
 def : WriteRes<WriteStoreNT, [SBPort23, SBPort4]>;
 def : WriteRes<WriteLoad,    [SBPort23]> { let Latency = 5; }
 def : WriteRes<WriteMove,    [SBPort015]>;
+def : InstRW<[WriteMove], (instrs COPY)>;
 def : WriteRes<WriteZero,    []>;
 def : WriteRes<WriteVecMaskedGatherWriteback, []> { let Latency = 5; let NumMicroOps = 0; }
 


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