[llvm] b6efd25 - [InstCombine] add tests for nsw propagation; NFC

[Roman Lebedev via llvm-commits]

Might be worth adding another false test where the outermost sub is
not a true negation.

Roman

On Wed, Mar 23, 2022 at 10:33 PM Sanjay Patel via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
>
>
> Author: Sanjay Patel
> Date: 2022-03-23T15:31:25-04:00
> New Revision: b6efd2510a1efaf2f48b7cd48a3db30b64ec7a51
>
> URL: https://github.com/llvm/llvm-project/commit/b6efd2510a1efaf2f48b7cd48a3db30b64ec7a51
> DIFF: https://github.com/llvm/llvm-project/commit/b6efd2510a1efaf2f48b7cd48a3db30b64ec7a51.diff
>
> LOG: [InstCombine] add tests for nsw propagation; NFC
>
> These are based on tests that were included in the abandoned D122299.
> Comments indicate what should or should not happen if we change
> behavior in Negator.
>
> Added:
>
>
> Modified:
>     llvm/test/Transforms/InstCombine/nsw.ll
>
> Removed:
>
>
>
> ################################################################################
> diff  --git a/llvm/test/Transforms/InstCombine/nsw.ll b/llvm/test/Transforms/InstCombine/nsw.ll
> index 52ecea598978d..4842a2139e120 100644
> --- a/llvm/test/Transforms/InstCombine/nsw.ll
> +++ b/llvm/test/Transforms/InstCombine/nsw.ll
> @@ -140,3 +140,89 @@ define <vscale x 2 x i64> @mul_nuw_nsw_shuffle_constant_expr(<vscale x 2 x i8> %
>    %t3 = mul <vscale x 2 x i64> %shuf, %xx
>    ret <vscale x 2 x i64> %t3
>  }
> +
> +; This could propagate nsw.
> +
> +define i32 @neg_sub0_sub_nsw_nsw(i32 %a, i32 %b) {
> +; CHECK-LABEL: @neg_sub0_sub_nsw_nsw(
> +; CHECK-NEXT:    [[C_NEG:%.*]] = sub i32 [[B:%.*]], [[A:%.*]]
> +; CHECK-NEXT:    ret i32 [[C_NEG]]
> +;
> +  %c = sub nsw i32 %a, %b
> +  %d = sub nsw i32 0, %c
> +  ret i32 %d
> +}
> +
> +; Must not propagate nsw.
> +
> +define i32 @neg_sub_sub_nsw0(i32 %a, i32 %b) {
> +; CHECK-LABEL: @neg_sub_sub_nsw0(
> +; CHECK-NEXT:    [[C_NEG:%.*]] = sub i32 [[B:%.*]], [[A:%.*]]
> +; CHECK-NEXT:    ret i32 [[C_NEG]]
> +;
> +  %c = sub nsw i32 %a, %b
> +  %d = sub i32 0, %c
> +  ret i32 %d
> +}
> +
> +; Must not propagate nsw.
> +
> +define i32 @neg_sub_sub_nsw1(i32 %a, i32 %b) {
> +; CHECK-LABEL: @neg_sub_sub_nsw1(
> +; CHECK-NEXT:    [[C_NEG:%.*]] = sub i32 [[B:%.*]], [[A:%.*]]
> +; CHECK-NEXT:    ret i32 [[C_NEG]]
> +;
> +  %c = sub i32 %a, %b
> +  %d = sub nsw i32 0, %c
> +  ret i32 %d
> +}
> +
> +; This could propagate nsw.
> +
> +define i32 @neg_mul_sub_nsw_nsw(i32 %a, i32 %b) {
> +; CHECK-LABEL: @neg_mul_sub_nsw_nsw(
> +; CHECK-NEXT:    [[C_NEG:%.*]] = sub i32 [[B:%.*]], [[A:%.*]]
> +; CHECK-NEXT:    ret i32 [[C_NEG]]
> +;
> +  %c = sub nsw i32 %a, %b
> +  %d = mul nsw i32 -1, %c
> +  ret i32 %d
> +}
> +
> +; Must not propagate nsw.
> +
> +define i32 @neg_mul_sub_nsw0(i32 %a, i32 %b) {
> +; CHECK-LABEL: @neg_mul_sub_nsw0(
> +; CHECK-NEXT:    [[C_NEG:%.*]] = sub i32 [[B:%.*]], [[A:%.*]]
> +; CHECK-NEXT:    ret i32 [[C_NEG]]
> +;
> +  %c = sub nsw i32 %a, %b
> +  %d = mul i32 -1, %c
> +  ret i32 %d
> +}
> +
> +; Must not propagate nsw.
> +
> +define i32 @neg_mul_sub_nsw1(i32 %a, i32 %b) {
> +; CHECK-LABEL: @neg_mul_sub_nsw1(
> +; CHECK-NEXT:    [[C_NEG:%.*]] = sub i32 [[B:%.*]], [[A:%.*]]
> +; CHECK-NEXT:    ret i32 [[C_NEG]]
> +;
> +  %c = sub i32 %a, %b
> +  %d = mul nsw i32 -1, %c
> +  ret i32 %d
> +}
> +
> +; Must not propagate nsw.
> +
> +define i8 @neg_sub_sub2(i16 %a, i16 %b) {
> +; CHECK-LABEL: @neg_sub_sub2(
> +; CHECK-NEXT:    [[C_NEG:%.*]] = sub i16 [[B:%.*]], [[A:%.*]]
> +; CHECK-NEXT:    [[D_NEG:%.*]] = trunc i16 [[C_NEG]] to i8
> +; CHECK-NEXT:    ret i8 [[D_NEG]]
> +;
> +  %c = sub nsw i16 %a, %b
> +  %d = trunc i16 %c to i8
> +  %e = sub nsw i8 0, %d
> +  ret i8 %e
> +}
>
>
>
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