[llvm] b75399a - [InstCombine] Add some initial SimplifyDemandedBits tests for removal of ashr with sufficient signbits

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-03-23T19:07:10Z
New Revision: b75399a5e20f51b9d2fa89c68575e0564a8eede6

URL: https://github.com/llvm/llvm-project/commit/b75399a5e20f51b9d2fa89c68575e0564a8eede6
DIFF: https://github.com/llvm/llvm-project/commit/b75399a5e20f51b9d2fa89c68575e0564a8eede6.diff

LOG: [InstCombine] Add some initial SimplifyDemandedBits tests for removal of ashr with sufficient signbits

We have this in SelectionDAG but it's missing in InstCombine

Based off PR21929 test case

Added: 
    llvm/test/Transforms/InstCombine/ashr-demand.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/ashr-demand.ll b/llvm/test/Transforms/InstCombine/ashr-demand.ll
new file mode 100644
index 0000000000000..4ec973ca24e2e
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/ashr-demand.ll
@@ -0,0 +1,56 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -passes=instcombine -S < %s | FileCheck %s
+
+; If we only want bits that already match the signbit then we don't need to shift.
+
+define i32 @srem2_ashr_mask(i32 %a0) {
+; CHECK-LABEL: @srem2_ashr_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[A0:%.*]], -2147483647
+; CHECK-NEXT:    [[ISNEG:%.*]] = icmp eq i32 [[TMP1]], -2147483647
+; CHECK-NEXT:    [[MASK:%.*]] = select i1 [[ISNEG]], i32 2, i32 0
+; CHECK-NEXT:    ret i32 [[MASK]]
+;
+  %srem = srem i32 %a0, 2 ; result = (1,0,-1) num signbits = 31
+  %ashr = ashr i32 %srem, 31
+  %mask = and i32 %ashr, 2
+  ret i32 %mask
+}
+
+define i32 @srem8_ashr_mask(i32 %a0) {
+; CHECK-LABEL: @srem8_ashr_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[A0:%.*]], -2147483641
+; CHECK-NEXT:    [[ISNEG:%.*]] = icmp ugt i32 [[TMP1]], -2147483648
+; CHECK-NEXT:    [[MASK:%.*]] = select i1 [[ISNEG]], i32 2, i32 0
+; CHECK-NEXT:    ret i32 [[MASK]]
+;
+  %srem = srem i32 %a0, 8
+  %ashr = ashr i32 %srem, 31
+  %mask = and i32 %ashr, 2
+  ret i32 %mask
+}
+
+define <2 x i32> @srem2_ashr_mask_vector(<2 x i32> %a0) {
+; CHECK-LABEL: @srem2_ashr_mask_vector(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i32> [[A0:%.*]], <i32 -2147483647, i32 -2147483647>
+; CHECK-NEXT:    [[ISNEG:%.*]] = icmp eq <2 x i32> [[TMP1]], <i32 -2147483647, i32 -2147483647>
+; CHECK-NEXT:    [[MASK:%.*]] = select <2 x i1> [[ISNEG]], <2 x i32> <i32 2, i32 2>, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x i32> [[MASK]]
+;
+  %srem = srem <2 x i32> %a0, <i32 2, i32 2>
+  %ashr = ashr <2 x i32> %srem, <i32 31, i32 31>
+  %mask = and <2 x i32> %ashr, <i32 2, i32 2>
+  ret <2 x i32> %mask
+}
+
+define <2 x i32> @srem2_ashr_mask_vector_nonconstant(<2 x i32> %a0, <2 x i32> %a1) {
+; CHECK-LABEL: @srem2_ashr_mask_vector_nonconstant(
+; CHECK-NEXT:    [[SREM:%.*]] = srem <2 x i32> [[A0:%.*]], <i32 2, i32 2>
+; CHECK-NEXT:    [[ASHR:%.*]] = ashr <2 x i32> [[SREM]], [[A1:%.*]]
+; CHECK-NEXT:    [[MASK:%.*]] = and <2 x i32> [[ASHR]], <i32 2, i32 2>
+; CHECK-NEXT:    ret <2 x i32> [[MASK]]
+;
+  %srem = srem <2 x i32> %a0, <i32 2, i32 2>
+  %ashr = ashr <2 x i32> %srem, %a1
+  %mask = and <2 x i32> %ashr, <i32 2, i32 2>
+  ret <2 x i32> %mask
+}