[PATCH] D122290: [RISCV] Remove check and update test file in D121183

[luxufan via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG5800fb41a6b9: [RISCV] Remove check and update test file in D121183 (authored by StephenFan).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122290/new/

https://reviews.llvm.org/D122290

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
  llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll
  llvm/test/MC/RISCV/mattr-invalid-combination.s


Index: llvm/test/MC/RISCV/mattr-invalid-combination.s
===================================================================
--- llvm/test/MC/RISCV/mattr-invalid-combination.s
+++ llvm/test/MC/RISCV/mattr-invalid-combination.s
@@ -1,4 +1,4 @@
 # RUN: not --crash llvm-mc -triple riscv64 -mattr=+e < %s 2>&1 \
 # RUN:   | FileCheck %s -check-prefix=RV64E
 
-# RV64E: LLVM ERROR: standard user-level extension 'e' requires 'rv32'
+# RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target
Index: llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll
===================================================================
--- llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll
+++ llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll
@@ -2,4 +2,4 @@
 ; RUN: not --crash llc -mtriple=riscv64 -mattr=+e < %s 2>&1 \
 ; RUN:   | FileCheck -check-prefix=RV64E %s
 
-; RV64E: LLVM ERROR: standard user-level extension 'e' requires 'rv32'
+; RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -80,16 +80,7 @@
   if (CPU.empty() || CPU == "generic")
     CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
 
-  MCSubtargetInfo *STI =
-      createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
-
-  // Check if Feature string is valid
-  auto ISAInfo =
-      RISCVFeatures::parseFeatureBits(TT.isArch64Bit(), STI->getFeatureBits());
-  if (!ISAInfo)
-    report_fatal_error(ISAInfo.takeError());
-  else
-    return STI;
+  return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
 }
 
 static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,


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