[PATCH] D122194: [SelectionDAG] Store LeadingZero count in LiveOutInfo instead of KnownBits.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D122194#3399209 <https://reviews.llvm.org/D122194#3399209>, @RKSimon wrote:

> How useful would it be to flip this - and generate some kind of ISD::AssertKnownBits node instead of ISD::AssertZext ?

I'm not sure. One case I do want to look at is trailing zeros for the reccurrence case that shows up in loop unrolling.

  loop:
     X = phi [0, preheader], [X.increment, loop]
     ...
     or X, 1
     ...
     or X, 2
     ...
     or X, 3
     ...
     X.increment = add X, 4
     ...
     br loop

X has 2 trailing zero bits so the ORs can be converted back to ADDs.

Adding a trailing zeros field is a straightforward extension to this patch and is still less storage than the 2 APInts. I think we might be able to reuse the AssertAlign node for it.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D122194/new/

https://reviews.llvm.org/D122194