[PATCH] D122219: [AMDGPU] [NFC]: Organize the code around reserving registers.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:670
+
+  // On GFX90A, the number of VGPRs and AGPRs need not be equal. Theoritically,a
+  // wave may have up to 512 total vector registers combining together both
----------------
Typo Theoritically


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  https://reviews.llvm.org/D122219/new/

https://reviews.llvm.org/D122219