[llvm] 7636c9a - [AMDGPU] use scalar shift for SALU users in frame index elimination

[via llvm-commits]

Author: alex-t
Date: 2022-03-22T13:16:24+01:00
New Revision: 7636c9a9297d82559a342d2c18a1205d7d7715c6

URL: https://github.com/llvm/llvm-project/commit/7636c9a9297d82559a342d2c18a1205d7d7715c6
DIFF: https://github.com/llvm/llvm-project/commit/7636c9a9297d82559a342d2c18a1205d7d7715c6.diff

LOG: [AMDGPU] use scalar shift for SALU users in frame index elimination

In the frame index lowering we have to insert shift and add
instructions to adjust stack object access.  We need to take care of the stack
object user kind and use scalar shift/add for scalar users.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D121524

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index d6b9c9f787774..3d7d56ec71d28 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -2272,7 +2272,8 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
         } else {
           MachineInstrBuilder MIB;
           if (!IsSALU) {
-            if (MIB = TII->getAddNoCarry(*MBB, MI, DL, ResultReg, *RS)) {
+            if ((MIB = TII->getAddNoCarry(*MBB, MI, DL, ResultReg, *RS)) !=
+                nullptr) {
               // Reuse ResultReg in intermediate step.
               Register ScaledReg = ResultReg;