[PATCH] D122051: [RISCV] The immediate version of sgt/ugt lowering to slti/sltiu + xori

[LiqinWeng via Phabricator via llvm-commits]

Miss_Grape added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:355
+// A 12-bit signed immediate sub one where the imm range will be [-2049, 2046].
+def simm12_sub1 : ImmLeaf<XLenVT,
+  [{return (isInt<12>(Imm) && Imm != 2047) || Imm == -2049;}]>;
----------------
Miss_Grape wrote:
> benshi001 wrote:
> > benshi001 wrote:
> > > The zero value should be excluded, which is not needed to do `li`, and case just 
> > >  be used with the register `X0`.
> > I think
> > 
> > 1. The form `(-2049 <= Imm && Imm < 0) || (0 < Imm && Imm <= 2046)` is more clear.
> > 
> > 2. Do a further check that the imm node has only one use.
> I don't think we need to specifically consider the case of Imm == 0， riscv-gcc did not exclude it alone
done


================
Comment at: llvm/test/CodeGen/RISCV/float-fcmp-strict.ll:72
+; RV32I-NEXT:    slti a0, a0, 1
+; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
----------------
Miss_Grape wrote:
> khchen wrote:
> > It seems no any benefits in this case, is it expected?
> sgtz ---->slt rd, X0, rs2
> slt rd, 0 rs2 ---> slti + xori 
> which can reduce the usage of one register
If this is the case（sgtz x1，x1）, there is really no benefit，so I have excluded the case where the immediate value is 0


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122051/new/

https://reviews.llvm.org/D122051