[llvm] ecd7a01 - [RISCV] Add basic cost model for vector casting
Yeting Kuo via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 21 23:17:14 PDT 2022
Author: Yeting Kuo
Date: 2022-03-22T14:17:08+08:00
New Revision: ecd7a0132a344af1451d262e226fad3eeb233b84
URL: https://github.com/llvm/llvm-project/commit/ecd7a0132a344af1451d262e226fad3eeb233b84
DIFF: https://github.com/llvm/llvm-project/commit/ecd7a0132a344af1451d262e226fad3eeb233b84.diff
LOG: [RISCV] Add basic cost model for vector casting
To perform the cost model of vector casting, the patch consider most vector
casts as their scalar form and consider those vector form of free scalr castings
as 1.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D121771
Added:
llvm/test/Analysis/CostModel/RISCV/cast.ll
Modified:
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 62538ead7f988..5f797f1dae7f8 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -11,6 +11,7 @@
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "llvm/CodeGen/TargetLowering.h"
+#include <cmath>
using namespace llvm;
#define DEBUG_TYPE "riscvtti"
@@ -218,6 +219,53 @@ InstructionCost RISCVTTIImpl::getGatherScatterOpCost(
return NumLoads * MemOpCost;
}
+InstructionCost RISCVTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
+ Type *Src,
+ TTI::CastContextHint CCH,
+ TTI::TargetCostKind CostKind,
+ const Instruction *I) {
+ if (isa<VectorType>(Dst) && isa<VectorType>(Src)) {
+ // FIXME: Need to compute legalizing cost for illegal types.
+ if (!isTypeLegal(Src) || !isTypeLegal(Dst))
+ return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
+
+ // Skip if element size of Dst or Src is bigger than ELEN.
+ if (Src->getScalarSizeInBits() > ST->getMaxELENForFixedLengthVectors() ||
+ Dst->getScalarSizeInBits() > ST->getMaxELENForFixedLengthVectors())
+ return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
+
+ int ISD = TLI->InstructionOpcodeToISD(Opcode);
+ assert(ISD && "Invalid opcode");
+
+ // FIXME: Need to consider vsetvli and lmul.
+ int PowDiff = (int)Log2_32(Dst->getScalarSizeInBits()) -
+ (int)Log2_32(Src->getScalarSizeInBits());
+ switch (ISD) {
+ case ISD::SIGN_EXTEND:
+ case ISD::ZERO_EXTEND:
+ return 1;
+ case ISD::TRUNCATE:
+ case ISD::FP_EXTEND:
+ case ISD::FP_ROUND:
+ // Counts of narrow/widen instructions.
+ return std::abs(PowDiff);
+ case ISD::FP_TO_SINT:
+ case ISD::FP_TO_UINT:
+ case ISD::SINT_TO_FP:
+ case ISD::UINT_TO_FP:
+ if (std::abs(PowDiff) <= 1)
+ return 1;
+ // Backend could lower (v[sz]ext i8 to double) to vfcvt(v[sz]ext.f8 i8),
+ // so it only need two conversion.
+ if (Src->isIntOrIntVectorTy())
+ return 2;
+ // Counts of narrow/widen instructions.
+ return std::abs(PowDiff);
+ }
+ }
+ return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
+}
+
InstructionCost
RISCVTTIImpl::getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy,
bool IsUnsigned,
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index 56e9d32593e84..9088d4847f3d9 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -89,6 +89,11 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
TTI::TargetCostKind CostKind,
const Instruction *I);
+ InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
+ TTI::CastContextHint CCH,
+ TTI::TargetCostKind CostKind,
+ const Instruction *I = nullptr);
+
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy,
bool IsUnsigned,
TTI::TargetCostKind CostKind);
diff --git a/llvm/test/Analysis/CostModel/RISCV/cast.ll b/llvm/test/Analysis/CostModel/RISCV/cast.ll
new file mode 100644
index 0000000000000..9c05d6129aca2
--- /dev/null
+++ b/llvm/test/Analysis/CostModel/RISCV/cast.ll
@@ -0,0 +1,306 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
+; RUN: opt < %s -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh -riscv-v-vector-bits-min=256 -passes='print<cost-model>' -cost-kind=throughput 2>&1 -disable-output | FileCheck %s --check-prefix=RISCV32
+; RUN: opt < %s -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh -riscv-v-vector-bits-min=256 -passes='print<cost-model>' -cost-kind=throughput 2>&1 -disable-output | FileCheck %s --check-prefix=RISCV64
+
+define void @ext() {
+; RISCV32-LABEL: 'ext'
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4i8i16 = sext <4 x i8> undef to <4 x i16>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z4i8i16 = zext <4 x i8> undef to <4 x i16>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4i8i32 = sext <4 x i8> undef to <4 x i32>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z4i8i32 = zext <4 x i8> undef to <4 x i32>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4i8i64 = sext <4 x i8> undef to <4 x i64>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z4i8i64 = zext <4 x i8> undef to <4 x i64>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4i16i32 = sext <4 x i16> undef to <4 x i32>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z4i16i32 = zext <4 x i16> undef to <4 x i32>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4i16i64 = sext <4 x i16> undef to <4 x i64>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z4i16i64 = zext <4 x i16> undef to <4 x i64>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4i32i64 = sext <4 x i32> undef to <4 x i64>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z4i32i64 = zext <4 x i32> undef to <4 x i64>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s8i8i16 = sext <8 x i8> undef to <8 x i16>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z8i8i16 = zext <8 x i8> undef to <8 x i16>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s8i8i32 = sext <8 x i8> undef to <8 x i32>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z8i8i32 = zext <8 x i8> undef to <8 x i32>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s8i8i64 = sext <8 x i8> undef to <8 x i64>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z8i8i64 = zext <8 x i8> undef to <8 x i64>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s8i16i32 = sext <8 x i16> undef to <8 x i32>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z8i16i32 = zext <8 x i16> undef to <8 x i32>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s8i16i64 = sext <8 x i16> undef to <8 x i64>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z8i16i64 = zext <8 x i16> undef to <8 x i64>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+;
+; RISCV64-LABEL: 'ext'
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4i8i16 = sext <4 x i8> undef to <4 x i16>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z4i8i16 = zext <4 x i8> undef to <4 x i16>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4i8i32 = sext <4 x i8> undef to <4 x i32>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z4i8i32 = zext <4 x i8> undef to <4 x i32>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4i8i64 = sext <4 x i8> undef to <4 x i64>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z4i8i64 = zext <4 x i8> undef to <4 x i64>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4i16i32 = sext <4 x i16> undef to <4 x i32>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z4i16i32 = zext <4 x i16> undef to <4 x i32>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4i16i64 = sext <4 x i16> undef to <4 x i64>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z4i16i64 = zext <4 x i16> undef to <4 x i64>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4i32i64 = sext <4 x i32> undef to <4 x i64>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z4i32i64 = zext <4 x i32> undef to <4 x i64>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s8i8i16 = sext <8 x i8> undef to <8 x i16>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z8i8i16 = zext <8 x i8> undef to <8 x i16>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s8i8i32 = sext <8 x i8> undef to <8 x i32>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z8i8i32 = zext <8 x i8> undef to <8 x i32>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s8i8i64 = sext <8 x i8> undef to <8 x i64>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z8i8i64 = zext <8 x i8> undef to <8 x i64>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s8i16i32 = sext <8 x i16> undef to <8 x i32>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z8i16i32 = zext <8 x i16> undef to <8 x i32>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s8i16i64 = sext <8 x i16> undef to <8 x i64>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %z8i16i64 = zext <8 x i16> undef to <8 x i64>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+ %s4i8i16 = sext <4 x i8> undef to <4 x i16>
+ %z4i8i16 = zext <4 x i8> undef to <4 x i16>
+ %s4i8i32 = sext <4 x i8> undef to <4 x i32>
+ %z4i8i32 = zext <4 x i8> undef to <4 x i32>
+ %s4i8i64 = sext <4 x i8> undef to <4 x i64>
+ %z4i8i64 = zext <4 x i8> undef to <4 x i64>
+ %s4i16i32 = sext <4 x i16> undef to <4 x i32>
+ %z4i16i32 = zext <4 x i16> undef to <4 x i32>
+ %s4i16i64 = sext <4 x i16> undef to <4 x i64>
+ %z4i16i64 = zext <4 x i16> undef to <4 x i64>
+ %s4i32i64 = sext <4 x i32> undef to <4 x i64>
+ %z4i32i64 = zext <4 x i32> undef to <4 x i64>
+
+ %s8i8i16 = sext <8 x i8> undef to <8 x i16>
+ %z8i8i16 = zext <8 x i8> undef to <8 x i16>
+ %s8i8i32 = sext <8 x i8> undef to <8 x i32>
+ %z8i8i32 = zext <8 x i8> undef to <8 x i32>
+ %s8i8i64 = sext <8 x i8> undef to <8 x i64>
+ %z8i8i64 = zext <8 x i8> undef to <8 x i64>
+ %s8i16i32 = sext <8 x i16> undef to <8 x i32>
+ %z8i16i32 = zext <8 x i16> undef to <8 x i32>
+ %s8i16i64 = sext <8 x i16> undef to <8 x i64>
+ %z8i16i64 = zext <8 x i16> undef to <8 x i64>
+ ret void
+}
+
+define void @trunc() {
+; RISCV32-LABEL: 'trunc'
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4i8i16 = trunc <4 x i16> undef to <4 x i8>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s4i8i32 = trunc <4 x i32> undef to <4 x i8>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %s4i8i64 = trunc <4 x i64> undef to <4 x i8>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4i16i32 = trunc <4 x i32> undef to <4 x i16>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s4i16i64 = trunc <4 x i64> undef to <4 x i16>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4i32i64 = trunc <4 x i64> undef to <4 x i32>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+;
+; RISCV64-LABEL: 'trunc'
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4i8i16 = trunc <4 x i16> undef to <4 x i8>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s4i8i32 = trunc <4 x i32> undef to <4 x i8>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %s4i8i64 = trunc <4 x i64> undef to <4 x i8>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4i16i32 = trunc <4 x i32> undef to <4 x i16>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s4i16i64 = trunc <4 x i64> undef to <4 x i16>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4i32i64 = trunc <4 x i64> undef to <4 x i32>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+ %s4i8i16 = trunc <4 x i16> undef to <4 x i8>
+ %s4i8i32 = trunc <4 x i32> undef to <4 x i8>
+ %s4i8i64 = trunc <4 x i64> undef to <4 x i8>
+ %s4i16i32 = trunc <4 x i32> undef to <4 x i16>
+ %s4i16i64 = trunc <4 x i64> undef to <4 x i16>
+ %s4i32i64 = trunc <4 x i64> undef to <4 x i32>
+ ret void
+}
+
+define void @fpext() {
+; RISCV32-LABEL: 'fpext'
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = fpext <8 x half> undef to <8 x float>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v1 = fpext <8 x half> undef to <8 x double>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2 = fpext <8 x float> undef to <8 x double>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+;
+; RISCV64-LABEL: 'fpext'
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = fpext <8 x half> undef to <8 x float>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v1 = fpext <8 x half> undef to <8 x double>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2 = fpext <8 x float> undef to <8 x double>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+ %v0 = fpext <8 x half> undef to <8 x float>
+ %v1 = fpext <8 x half> undef to <8 x double>
+ %v2 = fpext <8 x float> undef to <8 x double>
+ ret void
+}
+
+define void @ftrunc() {
+; RISCV32-LABEL: 'ftrunc'
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = fptrunc <8 x float> undef to <8 x half>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v1 = fptrunc <8 x double> undef to <8 x half>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2 = fptrunc <8 x double> undef to <8 x float>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+;
+; RISCV64-LABEL: 'ftrunc'
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v0 = fptrunc <8 x float> undef to <8 x half>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v1 = fptrunc <8 x double> undef to <8 x half>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2 = fptrunc <8 x double> undef to <8 x float>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+ %v0 = fptrunc <8 x float> undef to <8 x half>
+ %v1 = fptrunc <8 x double> undef to <8 x half>
+ %v2 = fptrunc <8 x double> undef to <8 x float>
+ ret void
+}
+
+define void @fp_to_int() {
+; RISCV32-LABEL: 'fp_to_int'
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s0 = fptosi <4 x half> undef to <4 x i8>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s1 = fptosi <4 x float> undef to <4 x i8>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %s2 = fptosi <4 x double> undef to <4 x i8>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s3 = fptosi <4 x half> undef to <4 x i16>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4 = fptosi <4 x float> undef to <4 x i16>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s5 = fptosi <4 x double> undef to <4 x i16>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s6 = fptosi <4 x half> undef to <4 x i32>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s7 = fptosi <4 x float> undef to <4 x i32>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s8 = fptosi <4 x double> undef to <4 x i32>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s9 = fptosi <4 x half> undef to <4 x i64>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s10 = fptosi <4 x float> undef to <4 x i64>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s11 = fptosi <4 x double> undef to <4 x i16>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u0 = fptoui <4 x half> undef to <4 x i8>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %u1 = fptoui <4 x float> undef to <4 x i8>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %u2 = fptoui <4 x double> undef to <4 x i8>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u3 = fptoui <4 x half> undef to <4 x i16>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u4 = fptoui <4 x float> undef to <4 x i16>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %u5 = fptoui <4 x double> undef to <4 x i16>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u6 = fptoui <4 x half> undef to <4 x i32>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u7 = fptoui <4 x float> undef to <4 x i32>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u8 = fptoui <4 x double> undef to <4 x i32>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %u9 = fptoui <4 x half> undef to <4 x i64>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u10 = fptoui <4 x float> undef to <4 x i64>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %u11 = fptoui <4 x double> undef to <4 x i16>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+;
+; RISCV64-LABEL: 'fp_to_int'
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s0 = fptosi <4 x half> undef to <4 x i8>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s1 = fptosi <4 x float> undef to <4 x i8>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %s2 = fptosi <4 x double> undef to <4 x i8>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s3 = fptosi <4 x half> undef to <4 x i16>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4 = fptosi <4 x float> undef to <4 x i16>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s5 = fptosi <4 x double> undef to <4 x i16>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s6 = fptosi <4 x half> undef to <4 x i32>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s7 = fptosi <4 x float> undef to <4 x i32>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s8 = fptosi <4 x double> undef to <4 x i32>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s9 = fptosi <4 x half> undef to <4 x i64>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s10 = fptosi <4 x float> undef to <4 x i64>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s11 = fptosi <4 x double> undef to <4 x i16>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u0 = fptoui <4 x half> undef to <4 x i8>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %u1 = fptoui <4 x float> undef to <4 x i8>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %u2 = fptoui <4 x double> undef to <4 x i8>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u3 = fptoui <4 x half> undef to <4 x i16>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u4 = fptoui <4 x float> undef to <4 x i16>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %u5 = fptoui <4 x double> undef to <4 x i16>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u6 = fptoui <4 x half> undef to <4 x i32>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u7 = fptoui <4 x float> undef to <4 x i32>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u8 = fptoui <4 x double> undef to <4 x i32>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %u9 = fptoui <4 x half> undef to <4 x i64>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u10 = fptoui <4 x float> undef to <4 x i64>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %u11 = fptoui <4 x double> undef to <4 x i16>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+ %s0 = fptosi <4 x half> undef to <4 x i8>
+ %s1 = fptosi <4 x float> undef to <4 x i8>
+ %s2 = fptosi <4 x double> undef to <4 x i8>
+ %s3 = fptosi <4 x half> undef to <4 x i16>
+ %s4 = fptosi <4 x float> undef to <4 x i16>
+ %s5 = fptosi <4 x double> undef to <4 x i16>
+ %s6 = fptosi <4 x half> undef to <4 x i32>
+ %s7 = fptosi <4 x float> undef to <4 x i32>
+ %s8 = fptosi <4 x double> undef to <4 x i32>
+ %s9 = fptosi <4 x half> undef to <4 x i64>
+ %s10 = fptosi <4 x float> undef to <4 x i64>
+ %s11 = fptosi <4 x double> undef to <4 x i16>
+
+ %u0 = fptoui <4 x half> undef to <4 x i8>
+ %u1 = fptoui <4 x float> undef to <4 x i8>
+ %u2 = fptoui <4 x double> undef to <4 x i8>
+ %u3 = fptoui <4 x half> undef to <4 x i16>
+ %u4 = fptoui <4 x float> undef to <4 x i16>
+ %u5 = fptoui <4 x double> undef to <4 x i16>
+ %u6 = fptoui <4 x half> undef to <4 x i32>
+ %u7 = fptoui <4 x float> undef to <4 x i32>
+ %u8 = fptoui <4 x double> undef to <4 x i32>
+ %u9 = fptoui <4 x half> undef to <4 x i64>
+ %u10 = fptoui <4 x float> undef to <4 x i64>
+ %u11 = fptoui <4 x double> undef to <4 x i16>
+ ret void
+}
+
+define void @int_to_fp() {
+; RISCV32-LABEL: 'int_to_fp'
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s0 = sitofp <4 x i8> undef to <4 x half>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s1 = sitofp <4 x i8> undef to <4 x float>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s2 = sitofp <4 x i8> undef to <4 x double>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s3 = sitofp <4 x i16> undef to <4 x half>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4 = sitofp <4 x i16> undef to <4 x float>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s5 = sitofp <4 x i16> undef to <4 x double>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s6 = sitofp <4 x i32> undef to <4 x half>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s7 = sitofp <4 x i32> undef to <4 x float>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s8 = sitofp <4 x i32> undef to <4 x double>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s9 = sitofp <4 x i64> undef to <4 x half>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s10 = sitofp <4 x i64> undef to <4 x float>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s11 = sitofp <4 x i16> undef to <4 x double>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u0 = uitofp <4 x i8> undef to <4 x half>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %u1 = uitofp <4 x i8> undef to <4 x float>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %u2 = uitofp <4 x i8> undef to <4 x double>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u3 = uitofp <4 x i16> undef to <4 x half>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u4 = uitofp <4 x i16> undef to <4 x float>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %u5 = uitofp <4 x i16> undef to <4 x double>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u6 = uitofp <4 x i32> undef to <4 x half>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u7 = uitofp <4 x i32> undef to <4 x float>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u8 = uitofp <4 x i32> undef to <4 x double>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %u9 = uitofp <4 x i64> undef to <4 x half>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u10 = uitofp <4 x i64> undef to <4 x float>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %u11 = uitofp <4 x i16> undef to <4 x double>
+; RISCV32-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+;
+; RISCV64-LABEL: 'int_to_fp'
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s0 = sitofp <4 x i8> undef to <4 x half>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s1 = sitofp <4 x i8> undef to <4 x float>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s2 = sitofp <4 x i8> undef to <4 x double>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s3 = sitofp <4 x i16> undef to <4 x half>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s4 = sitofp <4 x i16> undef to <4 x float>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s5 = sitofp <4 x i16> undef to <4 x double>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s6 = sitofp <4 x i32> undef to <4 x half>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s7 = sitofp <4 x i32> undef to <4 x float>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s8 = sitofp <4 x i32> undef to <4 x double>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s9 = sitofp <4 x i64> undef to <4 x half>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s10 = sitofp <4 x i64> undef to <4 x float>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s11 = sitofp <4 x i16> undef to <4 x double>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u0 = uitofp <4 x i8> undef to <4 x half>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %u1 = uitofp <4 x i8> undef to <4 x float>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %u2 = uitofp <4 x i8> undef to <4 x double>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u3 = uitofp <4 x i16> undef to <4 x half>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u4 = uitofp <4 x i16> undef to <4 x float>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %u5 = uitofp <4 x i16> undef to <4 x double>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u6 = uitofp <4 x i32> undef to <4 x half>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u7 = uitofp <4 x i32> undef to <4 x float>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u8 = uitofp <4 x i32> undef to <4 x double>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %u9 = uitofp <4 x i64> undef to <4 x half>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %u10 = uitofp <4 x i64> undef to <4 x float>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %u11 = uitofp <4 x i16> undef to <4 x double>
+; RISCV64-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
+ %s0 = sitofp <4 x i8> undef to <4 x half>
+ %s1 = sitofp <4 x i8> undef to <4 x float>
+ %s2 = sitofp <4 x i8> undef to <4 x double>
+ %s3 = sitofp <4 x i16> undef to <4 x half>
+ %s4 = sitofp <4 x i16> undef to <4 x float>
+ %s5 = sitofp <4 x i16> undef to <4 x double>
+ %s6 = sitofp <4 x i32> undef to <4 x half>
+ %s7 = sitofp <4 x i32> undef to <4 x float>
+ %s8 = sitofp <4 x i32> undef to <4 x double>
+ %s9 = sitofp <4 x i64> undef to <4 x half>
+ %s10 = sitofp <4 x i64> undef to <4 x float>
+ %s11 = sitofp <4 x i16> undef to <4 x double>
+
+ %u0 = uitofp <4 x i8> undef to <4 x half>
+ %u1 = uitofp <4 x i8> undef to <4 x float>
+ %u2 = uitofp <4 x i8> undef to <4 x double>
+ %u3 = uitofp <4 x i16> undef to <4 x half>
+ %u4 = uitofp <4 x i16> undef to <4 x float>
+ %u5 = uitofp <4 x i16> undef to <4 x double>
+ %u6 = uitofp <4 x i32> undef to <4 x half>
+ %u7 = uitofp <4 x i32> undef to <4 x float>
+ %u8 = uitofp <4 x i32> undef to <4 x double>
+ %u9 = uitofp <4 x i64> undef to <4 x half>
+ %u10 = uitofp <4 x i64> undef to <4 x float>
+ %u11 = uitofp <4 x i16> undef to <4 x double>
+ ret void
+}
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