[PATCH] D122209: [RISCV] Allocate argument floating-point registers first

[Wang Pengcheng via Phabricator via llvm-commits]

pcwang-thead updated this revision to Diff 417193.
pcwang-thead added a comment.

Fix typo.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122209/new/

https://reviews.llvm.org/D122209

Files:
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
  llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
  llvm/test/CodeGen/RISCV/calling-conv-half.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
  llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
  llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll
  llvm/test/CodeGen/RISCV/codemodel-lowering.ll
  llvm/test/CodeGen/RISCV/copysign-casts.ll
  llvm/test/CodeGen/RISCV/double-arith-strict.ll
  llvm/test/CodeGen/RISCV/double-arith.ll
  llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/double-calling-conv.ll
  llvm/test/CodeGen/RISCV/double-convert-strict.ll
  llvm/test/CodeGen/RISCV/double-convert.ll
  llvm/test/CodeGen/RISCV/double-imm.ll
  llvm/test/CodeGen/RISCV/double-mem.ll
  llvm/test/CodeGen/RISCV/double-previous-failure.ll
  llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
  llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
  llvm/test/CodeGen/RISCV/float-arith-strict.ll
  llvm/test/CodeGen/RISCV/float-arith.ll
  llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
  llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/float-convert-strict.ll
  llvm/test/CodeGen/RISCV/float-convert.ll
  llvm/test/CodeGen/RISCV/float-imm.ll
  llvm/test/CodeGen/RISCV/float-mem.ll
  llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
  llvm/test/CodeGen/RISCV/fp-imm.ll
  llvm/test/CodeGen/RISCV/half-arith-strict.ll
  llvm/test/CodeGen/RISCV/half-arith.ll
  llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/half-convert-strict.ll
  llvm/test/CodeGen/RISCV/half-convert.ll
  llvm/test/CodeGen/RISCV/half-fcmp.ll
  llvm/test/CodeGen/RISCV/half-imm.ll
  llvm/test/CodeGen/RISCV/half-intrinsics.ll
  llvm/test/CodeGen/RISCV/half-mem.ll
  llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
  llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
  llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
  llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll
  llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
  llvm/test/CodeGen/RISCV/module-target-abi.ll
  llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
  llvm/test/CodeGen/RISCV/rv64f-float-convert.ll
  llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll
  llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
  llvm/test/CodeGen/RISCV/select-const.ll
  llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
  llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
  llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll
  llvm/test/CodeGen/RISCV/vararg.ll
  llvm/test/CodeGen/RISCV/zfh-imm.ll

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