[PATCH] D122208: [RISCV] Optimize (select Cond, X, 0) --> and (sext Cond), X

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll:21
 ; RV64:       # %bb.0:
-; RV64-NEXT:    srai a0, a0, 63
+; RV64-NEXT:    slti a0, a0, 0
+; RV64-NEXT:    negw a0, a0
----------------
This is clearly worse


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122208/new/

https://reviews.llvm.org/D122208