[PATCH] D120226: [RISCV] Support mask policy for RVV IR intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM other than those last comments.



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Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:513
+  bool UsesMaskPolicy = RISCVII::UsesMaskPolicy(TSFlags);
+  // FIXME: Could we look at the above or below instructions to choose the matched
+  // mask policy to reduce vsetvli instructions?
----------------
clang-format


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:523
     const MachineOperand &Op = MI.getOperand(MI.getNumExplicitOperands() - 1);
-    TailAgnostic = Op.getImm() & 0x1;
-  }
-
-  unsigned UseOpIdx;
-  if (!(ForceTailAgnostic || (HasPolicy && TailAgnostic)) &&
-      MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
+    int64_t Policy = Op.getImm();
+    assert(Policy <= (RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC) &&
----------------
use uint64_t so the assert won't allow negative numbers?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120226/new/

https://reviews.llvm.org/D120226