[PATCH] D122208: [RISCV] Optimize (select Cond, X, 0) --> and (sext Cond), X

[luxufan via Phabricator via llvm-commits]

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Add target dependent DAG combine for select node. The optimization is transform
`select Cond, X, 0` to `and (sext Cond), X`. For RISCV, this optimization can decrease 
code size. Other Arch(like X86) seems not. So I didn't add this optimization to generic
DAG Combine.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D122208

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/alu64.ll
  llvm/test/CodeGen/RISCV/fpclamptosat.ll
  llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
  llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
  llvm/test/CodeGen/RISCV/shifts.ll
  llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll

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